Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment
    22.
    发明申请
    Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment 失效
    控制电源管理环境中虚拟处理器空闲状态退出的深度和延迟

    公开(公告)号:US20110154323A1

    公开(公告)日:2011-06-23

    申请号:US12645597

    申请日:2009-12-23

    CPC classification number: G06F9/45533 G06F9/45541 G06F2009/45575

    Abstract: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

    Abstract translation: 在逻辑分区的数据处理系统中提供一种机制,用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息(CLSI)数据。 响应于引导逻辑分区,虚拟化层将CLSI数据传送到逻辑分区的操作系统(OS)。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS,OS将虚拟处理器的特定空闲状态传送到虚拟化层,以将特定的空闲状态和唤醒特性分配给虚拟处理器。

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