公开(公告)号：US08055005B2

公开(公告)日：2011-11-08

申请号：US11797308

申请日：2007-05-02

Applicant: Chun-Hsin Liu ,  Chung-Chun Wu ,  Jui-Chi Liao

Inventor： Chun-Hsin Liu ,  Chung-Chun Wu ,  Jui-Chi Liao

IPC: H04R25/00 ,  H04R9/08 ,  H04R11/04 ,  H04R17/02 ,  H04R19/04 ,  H04R21/02 ,  H04R1/00 ,  A45F5/00 ,  A45F3/14

CPC classification number: A45F5/00 ,  A45F2005/006 ,  Y10T24/1374 ,  Y10T24/1394

Abstract: A Bluetooth earphone and a lanyard structure thereof are provided. The Bluetooth earphone includes an earphone body and a lanyard structure. The lanyard structure includes a lanyard and a clip element. The lanyard is disposed on the clip element. The clip element includes two hooks gripping the earphone body for combining the lanyard structure with the earphone body.

Abstract translation: 提供蓝牙耳机及其挂绳结构。 蓝牙耳机包括耳机主体和挂绳结构。 挂绳结构包括挂绳和夹子元件。 挂绳安装在夹子上。 夹子元件包括抓住耳机主体的两个钩子，用于将挂绳结构与耳机主体组合。

公开(公告)号：US20090243981A1

公开(公告)日：2009-10-01

申请号：US12185821

申请日：2008-08-05

Applicant: Yung-Chih Chen ,  Chun-Hsin Liu ,  Po-Yuan Liu ,  Min-Feng Chiang

Inventor： Yung-Chih Chen ,  Chun-Hsin Liu ,  Po-Yuan Liu ,  Min-Feng Chiang

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/006 ,  G09G2330/08

Abstract: A driving module drives a display device having a plurality of pixel switches. The driving module includes a gate driving circuit, a plurality of switch components, and a shorting line. The gate driving circuit includes a plurality of output ends correspondingly coupled to the plurality of the pixel switches through a plurality of gate lines for outputting a plurality of gate driving signals and turning on the plurality of the pixel switches. The plurality of the gate lines are coupled to the shorting line through the switch components. Each control end of the switch components is coupled to the gate driving circuit for receiving the gate driving signals in order to refresh the state of the switch components.

Abstract translation: 驱动模块驱动具有多个像素开关的显示装置。 驱动模块包括栅极驱动电路，多个开关部件和短路线。 栅极驱动电路包括通过多条栅极线对应地耦合到多个像素开关的多个输出端，用于输出多个栅极驱动信号并导通多个像素开关。 多个栅极线通过开关部件耦合到短路线。 开关部件的每个控制端耦合到栅极驱动电路，用于接收栅极驱动信号，以刷新开关部件的状态。

公开(公告)号：US20070232233A1

公开(公告)日：2007-10-04

申请号：US11551238

申请日：2006-10-20

Applicant: Liang-Yi Liu ,  Chun-Hsin Liu ,  Shih-Wei Fang ,  Kuo-Ching Chang ,  Yu-Chang Hung ,  Chung-Peng Tsai

Inventor： Liang-Yi Liu ,  Chun-Hsin Liu ,  Shih-Wei Fang ,  Kuo-Ching Chang ,  Yu-Chang Hung ,  Chung-Peng Tsai

IPC: H04B7/00 ,  H04M1/00

CPC classification number: H04M1/7258 ,  H04M1/2535 ,  H04M1/72502 ,  H04M1/7253 ,  H04M2250/02 ,  H04W80/00 ,  H04W84/18 ,  H04W88/02

Abstract: A wireless handset includes: a Bluetooth RF module for performing wireless communication with a Voice over Internet Protocol (VoIP) communication device having Bluetooth communication functionality; a processing circuit, coupled to the Bluetooth RF module, for remotely controlling a VoIP software application, which is embedded in the VoIP communication device, through the Bluetooth RF module according to Bluetooth Human Interface Device specifications; and an audio input/output module, coupled to the processing circuit, for receiving audio waves to input an audio signal into the processing circuit, and/or outputting audio waves; wherein the wireless handset provides web phone communication functionality by utilizing the VoIP software application.

Abstract translation: 无线手持机包括：用于与具有蓝牙通信功能的具有互联网协议语音（VoIP）通信设备的无线通信的蓝牙RF模块; 耦合到蓝牙RF模块的处理电路，用于通过蓝牙RF模块根据蓝牙人机接口设备规格远程控制嵌入在VoIP通信设备中的VoIP软件应用; 以及音频输入/输出模块，耦合到处理电路，用于接收音频波以将音频信号输入到处理电路中和/或输出音频波; 其中所述无线手机通过利用所述VoIP软件应用来提供网络电话通信功能。

公开(公告)号：US09087492B2

公开(公告)日：2015-07-21

申请号：US13453581

申请日：2012-04-23

Applicant: Chun Huan Chang ,  Chun-Hsin Liu ,  Kun-Yueh Lin ,  Ya-Ting Lin

Inventor： Chun Huan Chang ,  Chun-Hsin Liu ,  Kun-Yueh Lin ,  Ya-Ting Lin

IPC: G06F3/038 ,  G09G3/36 ,  G06F17/50 ,  G06F1/10

CPC classification number: G09G3/3677 ,  G06F1/10 ,  G06F17/5077 ,  G09G2300/0426 ,  G09G2310/0205

Abstract: A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Abstract translation: 公开了一种在显示面板中使用的方法。 该方法包括在总线区域中提供M个总线线路，用于接收多个时钟信号，M为大于3的正整数; 提供多条信号线，以将来自M总线的时钟信号分别提供给电路区域，电路区域被配置为响应于时钟信号提供多个顺序的栅极线信号，多个信号线包括多个 相邻的信号线对，每个相邻的信号线对具有电阻差，所述信号线包括最大电阻值和最小电阻值，并且其中M总线布置成使得所述M个总线线路中的任一个中的电阻差 相邻的信号线对小于最大电阻值和最小电阻值之间的值差。

公开(公告)号：US08890785B2

公开(公告)日：2014-11-18

申请号：US13449322

申请日：2012-04-18

Applicant: Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

Inventor： Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3659 ,  G09G3/2074 ,  G09G2310/0286

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Abstract translation: 提供显示面板及其栅极驱动电路。 栅极驱动电路包括多个移位寄存器。 每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元 控制信号。 这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。 基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

公开(公告)号：US08456454B2

公开(公告)日：2013-06-04

申请号：US12488946

申请日：2009-06-22

Applicant: Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

Inventor： Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

IPC: G06F3/038 ,  G09G5/00 ,  G02F1/1333

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2330/08 ,  G09G2330/12

Abstract: A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.

Abstract translation: 公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。 具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。 扫描线分别连接到移位寄存器以驱动多个显示单元。 第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

公开(公告)号：US08320602B2

公开(公告)日：2012-11-27

申请号：US12116963

申请日：2008-05-08

Applicant: Chun-Hsin Liu ,  Shu-Yuan Cheng ,  Liang-Yi Liu

Inventor： Chun-Hsin Liu ,  Shu-Yuan Cheng ,  Liang-Yi Liu

IPC: H04R25/00

CPC classification number: H04R1/1066 ,  H04R1/1008 ,  H04R2201/109 ,  H04R2420/07

Abstract: An earphone includes a body with a surrounding side, a rotatable loop and an ear hook. The rotatable loop is pivotally connected with the body on two opposite ends of the surrounding side. The body and the rotatable loop can rotate with respect to a first axis and with respect to each other. The ear hook is pivotally mounted on one side of the rotatable loop near where the rotatable loop is connected with the body, and the ear hook can rotate with respect to a second axis, which is different from the first axis.

Abstract translation: 耳机包括具有环绕侧的主体，可旋转环和耳钩。 可旋转的环与主体在周围的两个相对的端部枢转地连接。 主体和可旋转环可以相对于第一轴线相对于彼此旋转。 耳钩可旋转地安装在可旋转环的一侧，可旋转环与主体相连接，耳钩可以相对于与第一轴不同的第二轴旋转。

公开(公告)号：US08175215B2

公开(公告)日：2012-05-08

申请号：US12572247

申请日：2009-10-01

Applicant: Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

Inventor： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

IPC: G11C19/00

CPC classification number: G11C19/28

Abstract: A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

Abstract translation: 移位寄存器包括多个级联连接级。 每一级响应于时钟信号和第一控制信号产生输出信号。 每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。 上拉模块用于根据时钟信号提供输出信号。 上拉驱动模块响应于第一控制信号而导通上拉模块。 第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。 第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。 第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

公开(公告)号：US08049828B2

公开(公告)日：2011-11-01

申请号：US12178662

申请日：2008-07-24

Applicant: Chun-Hsin Liu ,  Yung-Chih Chen ,  Po-Yuan Liu ,  Tsung-Ting Tsai

Inventor： Chun-Hsin Liu ,  Yung-Chih Chen ,  Po-Yuan Liu ,  Tsung-Ting Tsai

IPC: G02F1/1333 ,  G02F1/1345

CPC classification number: G02F1/1362 ,  G02F1/13454 ,  G02F1/136286 ,  G02F2001/136254 ,  G02F2203/69

Abstract: A flat-panel display device having test architecture is disclosed for disposing shorting bars without sacrificing wiring-on-array bus layout area of the outer-lead-bonding region. The flat-panel display device essentially includes a substrate having a plurality of driving integrated-circuit (IC) mounting areas, a plurality of signal lines and transmission lines disposed on the substrate, and a plurality of shorting bars disposed on the driving IC mounting areas. Each shorting bar is coupled to a corresponding signal line and a corresponding transmission line. Furthermore, in order to take out the laser-cutting process in the fabrication of the flat-panel display device for saving production cost, each driving IC mounting area is further disposed with a plurality of transistors for controlling the signal connections between the shorting bars and the signal lines, and also for controlling the signal connections between the shorting bars and the transmission lines.

Abstract translation: 公开了一种具有测试架构的平板显示装置，用于在不牺牲外引线接合区域的阵列总线布局面积的情况下设置短路棒。 平板显示装置基本上包括具有多个驱动集成电路（IC）安装区域的基板，设置在基板上的多条信号线和传输线以及设置在驱动IC安装区域上的多个短路棒 。 每个短路条耦合到对应的信号线和对应的传输线。 此外，为了在制造平板显示装置的同时取出激光切割工艺以节省生产成本，每个驱动IC安装区域还配置有多个晶体管，用于控制短路棒和短路棒之间的信号连接 信号线，并且还用于控制短路棒和传输线之间的信号连接。

公开(公告)号：US08027426B1

公开(公告)日：2011-09-27

申请号：US12837244

申请日：2010-07-15

Applicant: Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

Inventor： Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286 ,  G11C19/184

Abstract: An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.

Abstract translation: 示例性移位寄存器包括多个晶体管。 对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。 第一时钟信号和第二时钟信号相对于彼此相位反相。 第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。 而且，晶体管是负阈值电压晶体管。 在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。