公开(公告)号：US08653524B2

公开(公告)日：2014-02-18

申请号：US13446468

申请日：2012-04-13

Applicant: Po-Yuan Liu ,  Ming-Sheng Lai ,  Chun-Hsin Liu ,  Kun-Hua Tsai

Inventor： Po-Yuan Liu ,  Ming-Sheng Lai ,  Chun-Hsin Liu ,  Kun-Hua Tsai

IPC: H01L29/04

CPC classification number: G06F3/044 ,  G06F3/0412

Abstract: A touch panel display and method for manufacturing the same are disclosed. The touch panel display includes a first substrate, a second substrate, a touch-sensing member, and a liquid crystal layer. The first substrate has a first surface and a second surface thereon. The second substrate has an element array and is disposed on the second surface of the first substrate. The touch-sensing member locates on the first surface of the first substrate. Furthermore, the touch-sensing member includes a conductive layer, a patterned electrode layer, and a protective layer. The patterned electrode layer is correspondingly located on the periphery of the first substrate. The protective layer covers the conductive layer, and the patterned electrode layer. The conductive layer locates between the protective layer and the first substrate. In addition, the liquid crystal layer is disposed between the first and the second substrate.

Abstract translation: 公开了一种触摸面板显示器及其制造方法。 触摸面板显示器包括第一基板，第二基板，触摸感测部件和液晶层。 第一基板在其上具有第一表面和第二表面。 第二基板具有元件阵列并且设置在第一基板的第二表面上。 触摸感测部件位于第一基板的第一表面上。 此外，触摸感测构件包括导电层，图案化电极层和保护层。 图案化电极层相应地位于第一基板的周边上。 保护层覆盖导电层和图案化的电极层。 导电层位于保护层和第一基底之间。 此外，液晶层设置在第一和第二基板之间。

公开(公告)号：US08493376B2

公开(公告)日：2013-07-23

申请号：US12652154

申请日：2010-01-05

Applicant: Kuo-Chang Su ,  Chun-Hsin Liu ,  Min-Feng Chiang

Inventor： Kuo-Chang Su ,  Chun-Hsin Liu ,  Min-Feng Chiang

IPC: G06F3/038 ,  G06G5/00

CPC classification number: G02F1/136259 ,  B23K26/0006 ,  B23K2103/56 ,  G09G3/006 ,  G09G3/3688 ,  Y10T29/49718

Abstract: Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected.

Abstract translation: 公开了集成在显示面板中的驱动器电路结构。 驱动器电路结构包括多个晶体管和备用晶体管。 在完成驱动器电路结构之后，本公开检查它以找到一个无效晶体管。 检查过程首先将非活性晶体管与第一电极线之间的电连接和/或非活性晶体管与第二电极线之间的电连接隔离。 接下来，备用晶体管的源电极和第一电极线和/或电连接备用晶体管的漏电极和第二电极线电连接。

公开(公告)号：US08331524B2

公开(公告)日：2012-12-11

申请号：US13110948

申请日：2011-05-19

Applicant: Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kuo-Chang Su ,  Yu-Chung Yang

Inventor： Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kuo-Chang Su ,  Yu-Chung Yang

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract translation: 具有波形整形功能的移位寄存器电路包括多个移位寄存器级。 每个移位寄存器级包括第一输入单元，上拉单元，下拉电路，第二输入单元，控制单元和波形整形单元。 第一输入单元用于响应于第一门信号输出第一驱动控制电压。 上拉单元响应于第一驱动控制电压拉起第二门信号。 下拉电路用于下拉第一驱动控制电压和第二栅极信号。 第二输入单元用于响应于第一门信号输出第二驱动控制电压。 控制单元响应于第二驱动控制电压和辅助信号提供控制信号。 波形整形单元响应于控制信号对第二门信号执行波形整形操作。

公开(公告)号：US20120250816A1

公开(公告)日：2012-10-04

申请号：US13492916

申请日：2012-06-10

Applicant: Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

Inventor： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract translation: 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US20120140873A1

公开(公告)日：2012-06-07

申请号：US13372796

申请日：2012-02-14

Applicant: Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

Inventor： Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286 ,  G11C19/184

Abstract: An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors.

Abstract translation: 示例性移位寄存器包括控制电路和输出晶体管。 控制电路具有起始脉冲信号输入端，第一时钟脉冲信号输入端和电源电压输入端，并具有第一控制晶体管和第二控制晶体管。 输出晶体管电耦合到第一控制晶体管，并且包括栅极驱动信号输出端和第二时钟脉冲信号输入端。 此外，第一控制晶体管，第二控制晶体管和输出晶体管都是负阈值电压晶体管。

公开(公告)号：US20120134460A1

公开(公告)日：2012-05-31

申请号：US13090593

申请日：2011-04-20

Applicant: Ying-Chen CHEN ,  Hao-Chieh Lee ,  Chun-Huan Chang ,  Chun-Hsin Liu ,  Wan-Jung Chen

Inventor： Ying-Chen CHEN ,  Hao-Chieh Lee ,  Chun-Huan Chang ,  Chun-Hsin Liu ,  Wan-Jung Chen

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286

Abstract: An exemplary layout structure of a shift register circuit includes a first shift register and a second shift register arranged adjacent to the first shift register. The first shift register and the second shift register each receive a first signal and a second signal phase-inverted with respect to the first signal. Moreover, the first shift register and the second shift register share a common signal routing trace for receiving the first signal. The common signal routing trace is arranged extending into between the first shift register and the second shift register.

Abstract translation: 移位寄存器电路的示例性布局结构包括与第一移位寄存器相邻布置的第一移位寄存器和第二移位寄存器。 第一移位寄存器和第二移位寄存器各自接收相对于第一信号相位反转的第一信号和第二信号。 此外，第一移位寄存器和第二移位寄存器共享用于接收第一信号的公共信号路由跟踪。 公共信号路由跟踪被布置成延伸到第一移位寄存器和第二移位寄存器之间。

公开(公告)号：US08178383B2

公开(公告)日：2012-05-15

申请号：US12232846

申请日：2008-09-25

Applicant: Po-Yuan Liu ,  Ming-Sheng Lai ,  Chun-Hsin Liu ,  Kun-Hua Tsai

Inventor： Po-Yuan Liu ,  Ming-Sheng Lai ,  Chun-Hsin Liu ,  Kun-Hua Tsai

IPC: H01L21/00

CPC classification number: G06F3/044 ,  G06F3/0412

Abstract: A display device and method for manufacturing the same are disclosed. The display device includes a first substrate, a second substrate, a touch-sensing element, and a liquid crystal. The first substrate has a first surface and a second surface thereon. The second substrate has a pixel array and is disposed on the second surface of the first substrate. The touch-sensing element locates on the first surface of the first substrate. Furthermore, the touch-sensing element includes a conductive layer, a patterned electrode, and a passivation layer. The patterned electrode is correspondingly located on the periphery of the first substrate, and electrically connected to the conductive layer. The passivation layer covers the conductive layer and the patterned electrode. In addition, the liquid crystal is disposed between the first substrate and the second substrate.

Abstract translation: 公开了一种显示装置及其制造方法。 显示装置包括第一基板，第二基板，触摸感测元件和液晶。 第一基板在其上具有第一表面和第二表面。 第二基板具有像素阵列并且设置在第一基板的第二表面上。 触摸感测元件位于第一基板的第一表面上。 此外，触摸感测元件包括导电层，图案化电极和钝化层。 图案化电极相应地位于第一基板的周边上，并且电连接到导电层。 钝化层覆盖导电层和图案化电极。 此外，液晶设置在第一基板和第二基板之间。

公开(公告)号：US08139808B2

公开(公告)日：2012-03-20

申请号：US11802703

申请日：2007-05-24

Applicant: Chun-Hsin Liu ,  Chung-Chun Wu ,  Jui-Chi Liao

Inventor： Chun-Hsin Liu ,  Chung-Chun Wu ,  Jui-Chi Liao

IPC: H04R25/00

CPC classification number: H04R1/1066 ,  H04M1/05 ,  H04M1/6066 ,  H04R1/1016 ,  H04R1/1058 ,  H04R2201/107 ,  H04R2201/109 ,  H04R2420/07

Abstract: An ear hooked earphone is provided for selectively being worn on a left or right ear of a user. The earphone includes a body and an ear hook. The body includes a first coupled portion formed on a surface thereof. The ear hook includes a hook section and a fastened section. The hook section is used for hooking around the ear of the user. The fastened section is connected with the hook section, and a separation is formed between ends of the hook section and the fastened section. The fastened section has a second coupled portion, and one of two sides of the second coupled portion is selectively coupled with the first coupled section. Thereby, the position of the separation relative to the body is able to be changed, that is, the ear hooked earphone is able to hang on the left or right ear of the user freely.

Abstract translation: 提供耳挂式耳机，用于选择性地佩戴在使用者的左耳或右耳上。 耳机包括主体和耳钩。 主体包括形成在其表面上的第一联接部分。 耳钩包括钩部和紧固部。 挂钩部分用于钩住使用者的耳朵。 紧固部分与钩部连接，并且在钩部和紧固部的端部之间形成分离。 紧固部分具有第二联接部分，并且第二联接部分的两侧中的一个选择性地与第一联接部分联接。 因此，能够改变相对于身体的分离位置，即耳挂式耳机能够自由地悬挂在使用者的左耳或右耳上。

公开(公告)号：US08098792B2

公开(公告)日：2012-01-17

申请号：US12790854

申请日：2010-05-31

Applicant: Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin

Inventor： Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin

IPC: G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/28

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

公开(公告)号：US20110255652A1

公开(公告)日：2011-10-20

申请号：US13175475

申请日：2011-07-01

Applicant: Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

Inventor： Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286 ,  G11C19/184

Abstract: An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.

Abstract translation: 示例性移位寄存器包括控制电路和输出电路。 控制电路电耦合以接收起始脉冲信号，第一时钟脉冲信号和电源电压，并且用于根据起始脉冲信号和第一时钟脉冲信号产生使能信号。 第一时钟脉冲信号的逻辑低电平低于电源电压的电平。 对输出电路进行使能信号的控制，并根据第二时钟脉冲信号产生栅极驱动信号。 第二时钟脉冲信号和第一时钟脉冲信号相对于彼此相位反转，并且第二时钟脉冲信号的逻辑低电平高于电源电压的电平。