Efficient implementation of a filter

    公开(公告)号:US07398288B2

    公开(公告)日:2008-07-08

    申请号:US10651922

    申请日:2003-08-29

    IPC分类号: G06F17/10

    CPC分类号: H03H17/06

    摘要: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make K ⁡ [ ( L 1 + L 2 L 1 ⁢ L 2 ) ⁢ N + L 2 L 1 + 1 ] memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers. For an embodiment in which L1=L2=8, inner and outer loop code make K ⁡ ( N 4 + 2 ) memory accesses, which for filter implementations with large numbers of taps, approaches a 4× reduction in the number of memory accesses as compared to conventional methods.

    Impairment compensation sequence for communication
    22.
    发明授权
    Impairment compensation sequence for communication 有权
    减值补偿顺序为通讯

    公开(公告)号:US07397845B1

    公开(公告)日:2008-07-08

    申请号:US09627573

    申请日:2000-07-28

    申请人: Haixiang Liang

    发明人: Haixiang Liang

    IPC分类号: H04B1/38 H04L5/16

    CPC分类号: H04L25/4927

    摘要: An impairment compensation sequence for use in a communication system susceptible to one or more potential impairments each periodic in an integer number of symbols includes N phases, wherein N is selected such that each potential impairment, if present, is periodic therein, and a sequence of symbols, the sequence organized to place at least one instance of each symbol from a predetermined set of symbols in each phase to allow detection of the potential impairments in each of the N phases. The potential impairments may include robbed-bit signaling and padding. Using estimates prepared based on such an impairment compensation sequence, individual phase intervals may be grouped according to similarity of apparent aggregate effect of the impairments thereon without identification of individual impairments active in the particular phases. Constellation points may then be assigned based on group characteristics corresponding to phase intervals. In an exemplary realization, constellation points are assigned for each of 6 constellation indices based on amplitude estimates characteristic of the groups with which each of 4 corresponding phase intervals are associated.

    摘要翻译: 用于易受一个或多个潜在损伤的通信系统中的损伤补偿序列,每个周期性的整数符号包括N个相,其中选择N,使得每个潜在损伤(如果存在)在其中是周期性的, 符号,所述序列被组织以在每个相位中放置来自预定符号集合的每个符号的至少一个实例,以允许检测N个相中的每一个中的潜在损伤。 潜在的损害可能包括抢占信令和填充。 使用基于这样的损伤补偿顺序准备的估计,可以根据其上的损伤的表观总效应的相似度对各个相位间隔进行分组,而不识别在特定阶段中有活性的个体损伤。 然后可以基于对应于相位间隔的组特征来分配星座点。 在示例性实现中,基于与4个对应的相位间隔相关联的组的振幅估计特征,为6个星座索引中的每一个分配星座点。

    Non-iterative time-domain equalizer

    公开(公告)号:US20060062290A1

    公开(公告)日:2006-03-23

    申请号:US11265322

    申请日:2005-11-01

    申请人: Haixiang Liang

    发明人: Haixiang Liang

    IPC分类号: H03K5/159 H04B1/10

    摘要: A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z) and a residual output B(z) is chosen so that its degree is less than a cyclic prefix. An error signal is formed so that E(z)=H(z)A(z)−B(z). With a unit input, the error signal is set to zero and B(z)=H(z)A(z). Each signal is expressed as a polynomial, having varying degrees, and a having corresponding coefficients. Once expanded, the coefficients of similar degree can be equated on both sides of the equation. The error signal can then be determined in terms of coefficients corresponding to the TEQ and the residual signal. The coefficients of the channel response can be derived from the channel training estimates. The error signal is minimized and the result is solved for in terms of the desired TEQ coefficients.

    Non-iterative time-domain equalizer
    24.
    发明授权
    Non-iterative time-domain equalizer 失效
    非迭代时域均衡器

    公开(公告)号:US06961372B2

    公开(公告)日:2005-11-01

    申请号:US09929329

    申请日:2001-08-13

    申请人: Haixiang Liang

    发明人: Haixiang Liang

    IPC分类号: H04L25/03 H04B1/38 H04L25/08

    摘要: A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z) and a residual output B(z) is chosen so that its degree is less than a cyclic prefix. An error signal is formed so that E(z)=H(z)A(z)−B(z). With a unit input, the error signal is set to zero and B(z)=H(z)A(z). Each signal is expressed as a polynomial, having varying degrees, and a having corresponding coefficients. Once expanded, the coefficients of similar degree can be equated on both sides of the equation. The error signal can then be determined in terms of coefficients corresponding to the TEQ and the residual signal. The coefficients of the channel response can be derived from the channel training estimates. The error signal is minimized and the result is solved for in terms of the desired TEQ coefficients.

    摘要翻译: 一种用于形成非迭代时域均衡器(TEQ)的方法和与之对应的装置。 频道响应H(z)之后是TEQ响应A(z),并且选择剩余输出B(z),使得其度数小于循环前缀。 形成误差信号,使得E(z)= H(z)A(z)-B(z)。 使用单位输入,误差信号设置为零,B(z)= H(z)A(z)。 每个信号被表示为具有不同程度的多项式,并具有相应的系数。 一旦扩展,类似程度的系数可以等同于方程的两边。 然后可以根据对应于TEQ和残余信号的系数来确定误差信号。 信道响应的系数可以从信道训练估计导出。 误差信号被最小化,并且根据期望的TEQ系数求解结果。

    Digital filter implementation suitable for execution, together with application code, on a same processor
    25.
    发明授权
    Digital filter implementation suitable for execution, together with application code, on a same processor 失效
    适用于同一处理器的数字滤波器实现以及应用程序代码

    公开(公告)号:US06618739B1

    公开(公告)日:2003-09-09

    申请号:US09790281

    申请日:2001-02-22

    IPC分类号: G06F1710

    CPC分类号: H03H17/06

    摘要: A filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In some realizations, both application code and filter code are executed on a same general purpose processor. The filter code incrementally loads respective portions of input and coefficient vector data from addressable storage into respective registers of the processor and performs successive operations thereupon to accumulate output vector data into other respective registers of the processor. The filter code typically exhibits an execution ratio of less than two input and coefficient data loads per operation to accumulate. In some realizations, the filter code is callable from the application code and provides the application code with a signal processing facility without use of a digital signal processor (DSP).

    摘要翻译: 滤波器以通用处理器的软件以与传统方法相比减少存储器访问次数的方式实现。 在某些实现中,应用程序代码和过滤器代码都在相同的通用处理器上执行。 滤波器代码将来自可寻址存储器的输入和系数向量数据的相应部分递增地加载到处理器的相应寄存器中,并执行其上的连续操作,以将输出矢量数据累加到处理器的其他相应寄存器中。 滤波器代码通常表现出每个操作要累积的小于两个输入和系数数据负载的执行率。 在一些实现中,滤波器代码可以从应用代码调用,并且在不使用数字信号处理器(DSP)的情况下向应用代码提供信号处理设施。

    System and method for improving convergence during modem training and
reducing computational load during steady-state modem operations
    26.
    发明授权
    System and method for improving convergence during modem training and reducing computational load during steady-state modem operations 失效
    用于在调制解调器训练期间改善收敛并减少稳态调制解调器操作期间的计算负载的系统和方法

    公开(公告)号:US5864545A

    公开(公告)日:1999-01-26

    申请号:US761405

    申请日:1996-12-06

    IPC分类号: H04B3/23 H04B3/20

    CPC分类号: H04B3/235

    摘要: A phase-splitting T/3 equalizer and echo canceller structure is computationally efficient because only one point per baud is calculated. However, there are two drawbacks to the structure: (1) since the equalizer performs both the phase-splitting function and channel response equalization, its convergence is slow, and (2) when training the echo canceller during half-duplex training, an answering modem needs an assumed equalizer in its receive path to train its echo canceller, because the adaptive equalizer has not yet been trained; however, after equalizer training the echo canceller needs to be retrained because equalizer coefficients have changed. In contrast, a fixed phase splitting filter can be used during training. The echo canceller and equalizer are each trained with the fixed phase splitting filter thereby improving convergence performance, and after training, the equalizer is convolved with the fixed phase splitting filter to provide the combined phase splitting equalizer and the equalizer is convolved with the echo canceller to provide the combined echo canceller. In this way, computational load is small in steady state and convergence is fast during training. Even though the convergence rate is slower in data mode, it suitable for tracking line variations. An advantage of the transformation from the training structure to the steady-state structure is that a modem or system exploiting the technique provides improved convergence during training while reducing computational load during full-duplex operations. Half-duplex applications, i.e., modem or system operations without echo cancellation, similarly benefit from improved convergence during training and reduced computational load during steady-state operations.

    摘要翻译: 分相T / 3均衡器和回波消除器结构在计算上是有效的,因为每个波特率只计算一个点。 然而,结构有两个缺点:(1)均衡器既执行相位分割功能又实现信道响应均衡,其收敛速度较慢,(2)在半双工训练中训练回声消除器时,应答 调制解调器在其接收路径中需要一个假定的均衡器来训练其回声消除器,因为自适应均衡器尚未被训练; 然而,在均衡器训练之后,由于均衡器系数已经改变,回波消除器需要重新训练。 相比之下,在训练期间可以使用固定的分相滤波器。 回波消除器和均衡器每个都用固定相位分离滤波器进行训练,从而提高收敛性能,并且在训练之后,均衡器与固定相位分离滤波器卷积以提供组合分相均衡器,并且均衡器与回波消除器卷积到 提供组合的回声消除器。 这样,计算负荷在稳定状态下较小,训练过程中收敛速度较快。 即使在数据模式下收敛速度较慢,因此适用于跟踪线路变化。 从训练结构到稳态结构的转换的优点在于,利用该技术的调制解调器或系统在训练期间提供改进的收敛,同时减少全双工操作期间的计算负荷。 半双工应用,即没有回波消除的调制解调器或系统操作同样受益于在训练期间改进的收敛和在稳态操作期间减少的计算负荷。