摘要:
A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make K [ ( L 1 + L 2 L 1 L 2 ) N + L 2 L 1 + 1 ] memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers. For an embodiment in which L1=L2=8, inner and outer loop code make K ( N 4 + 2 ) memory accesses, which for filter implementations with large numbers of taps, approaches a 4× reduction in the number of memory accesses as compared to conventional methods.
摘要:
An impairment compensation sequence for use in a communication system susceptible to one or more potential impairments each periodic in an integer number of symbols includes N phases, wherein N is selected such that each potential impairment, if present, is periodic therein, and a sequence of symbols, the sequence organized to place at least one instance of each symbol from a predetermined set of symbols in each phase to allow detection of the potential impairments in each of the N phases. The potential impairments may include robbed-bit signaling and padding. Using estimates prepared based on such an impairment compensation sequence, individual phase intervals may be grouped according to similarity of apparent aggregate effect of the impairments thereon without identification of individual impairments active in the particular phases. Constellation points may then be assigned based on group characteristics corresponding to phase intervals. In an exemplary realization, constellation points are assigned for each of 6 constellation indices based on amplitude estimates characteristic of the groups with which each of 4 corresponding phase intervals are associated.
摘要:
A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z) and a residual output B(z) is chosen so that its degree is less than a cyclic prefix. An error signal is formed so that E(z)=H(z)A(z)−B(z). With a unit input, the error signal is set to zero and B(z)=H(z)A(z). Each signal is expressed as a polynomial, having varying degrees, and a having corresponding coefficients. Once expanded, the coefficients of similar degree can be equated on both sides of the equation. The error signal can then be determined in terms of coefficients corresponding to the TEQ and the residual signal. The coefficients of the channel response can be derived from the channel training estimates. The error signal is minimized and the result is solved for in terms of the desired TEQ coefficients.
摘要:
A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z) and a residual output B(z) is chosen so that its degree is less than a cyclic prefix. An error signal is formed so that E(z)=H(z)A(z)−B(z). With a unit input, the error signal is set to zero and B(z)=H(z)A(z). Each signal is expressed as a polynomial, having varying degrees, and a having corresponding coefficients. Once expanded, the coefficients of similar degree can be equated on both sides of the equation. The error signal can then be determined in terms of coefficients corresponding to the TEQ and the residual signal. The coefficients of the channel response can be derived from the channel training estimates. The error signal is minimized and the result is solved for in terms of the desired TEQ coefficients.
摘要:
A filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In some realizations, both application code and filter code are executed on a same general purpose processor. The filter code incrementally loads respective portions of input and coefficient vector data from addressable storage into respective registers of the processor and performs successive operations thereupon to accumulate output vector data into other respective registers of the processor. The filter code typically exhibits an execution ratio of less than two input and coefficient data loads per operation to accumulate. In some realizations, the filter code is callable from the application code and provides the application code with a signal processing facility without use of a digital signal processor (DSP).
摘要:
A phase-splitting T/3 equalizer and echo canceller structure is computationally efficient because only one point per baud is calculated. However, there are two drawbacks to the structure: (1) since the equalizer performs both the phase-splitting function and channel response equalization, its convergence is slow, and (2) when training the echo canceller during half-duplex training, an answering modem needs an assumed equalizer in its receive path to train its echo canceller, because the adaptive equalizer has not yet been trained; however, after equalizer training the echo canceller needs to be retrained because equalizer coefficients have changed. In contrast, a fixed phase splitting filter can be used during training. The echo canceller and equalizer are each trained with the fixed phase splitting filter thereby improving convergence performance, and after training, the equalizer is convolved with the fixed phase splitting filter to provide the combined phase splitting equalizer and the equalizer is convolved with the echo canceller to provide the combined echo canceller. In this way, computational load is small in steady state and convergence is fast during training. Even though the convergence rate is slower in data mode, it suitable for tracking line variations. An advantage of the transformation from the training structure to the steady-state structure is that a modem or system exploiting the technique provides improved convergence during training while reducing computational load during full-duplex operations. Half-duplex applications, i.e., modem or system operations without echo cancellation, similarly benefit from improved convergence during training and reduced computational load during steady-state operations.