公开(公告)号：USRE40138E1

公开(公告)日：2008-03-04

申请号：US10442631

申请日：2003-05-21

Applicant: Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

Inventor： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract translation: 已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。 该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。 在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料 当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。