公开(公告)号：US20190252381A1

公开(公告)日：2019-08-15

申请号：US16390744

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Hao Liu ,  Yan-Ming Tsai ,  Chung-Ting Wei ,  Ziwei Fang ,  Chih-Wei Chang ,  Chien-Hao Chen ,  Huicheng Chang

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/08

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.

公开(公告)号：US20190245035A1

公开(公告)日：2019-08-08

申请号：US15890077

申请日：2018-02-06

申请人： General Electric Company

发明人： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/761 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L29/0646 ,  H01L21/02529 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/1608

摘要： An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US20190214258A1

公开(公告)日：2019-07-11

申请号：US16207828

申请日：2018-12-03

申请人： Commissariat a l'energie atomique et aux energies alternatives

发明人： Frank FOURNEL ,  Frederic Mazen

IPC分类号： H01L21/18 ,  H01L21/324 ,  H01L21/265

CPC分类号： H01L21/187 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254

摘要： A process for attaching a first substrate to a second substrate by direct bonding includes the successive steps of: a) providing the first and second substrates, each comprising a first surface and an opposite second surface, b) bonding the first substrate to the second substrate by direct bonding between the first surfaces of the first and second substrates, step b) being carried out under a first gaseous atmosphere having a first relative humidity level denoted by φ1, and c) applying a thermal annealing treatment to the bonded first and second substrates at a thermal annealing temperature of between 20° C. and 700° C., step c) being carried out under a second gaseous atmosphere having a second humidity level denoted by φ2, satisfying φ2≥φ1.

公开(公告)号：US10347744B1

公开(公告)日：2019-07-09

申请号：US15865383

申请日：2018-01-09

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/66598 ,  H01L21/02252 ,  H01L21/26506 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66818 ,  H01L2029/7858

摘要： Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.

公开(公告)号：US20190189450A1

公开(公告)日：2019-06-20

申请号：US16216151

申请日：2018-12-11

申请人： NuFlare Technology, Inc.

发明人： Kiyotaka MIYANO

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L29/16

CPC分类号： H01L21/26506 ,  H01L21/02529 ,  H01L21/02612 ,  H01L21/324 ,  H01L29/1608

摘要： Provided is a method of manufacturing a semiconductor device according to an embodiment, including implanting carbon ions into a predetermined region of a silicon substrate; forming a silicon carbide layer on the silicon substrate by performing heat treatment on the silicon substrate implanted with the carbon ions; and removing at least a portion of the silicon substrate to expose the silicon carbide layer.

公开(公告)号：US20190157438A1

公开(公告)日：2019-05-23

申请号：US16254235

申请日：2019-01-22

申请人： Infineon Technologies AG

发明人： Hans-Joachim Schulze ,  Philip Christoph Brandt ,  Andre Rainer Stegner

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/167 ,  H01L21/24 ,  H01L21/266 ,  H01L29/66 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L29/7397 ,  H01L21/22 ,  H01L21/24 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/18 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/7396

摘要： Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm−3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm−3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.

公开(公告)号：US20190140004A1

公开(公告)日：2019-05-09

申请号：US16221850

申请日：2018-12-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Feng-Chi Hung ,  Jhy-Jyi Sze ,  Shou-Gwo Wuu

IPC分类号： H01L27/146 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L27/14616 ,  H01L21/0223 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/2822 ,  H01L21/76224 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/78

摘要： Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.

公开(公告)号：US10084087B2

公开(公告)日：2018-09-25

申请号：US15489423

申请日：2017-04-17

申请人： Intel Corporation

发明人： Cory E. Weber ,  Mark Y. Liu ,  Anand S. Murthy ,  Hemant V. Deshpande ,  Daniel B. Aubertine

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

公开(公告)号：US10062690B2

公开(公告)日：2018-08-28

申请号：US15209662

申请日：2016-07-13

申请人： STMICROELECTRONICS, INC.

发明人： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US10062569B2

公开(公告)日：2018-08-28

申请号：US15104692

申请日：2014-12-10

申请人： SUMCO CORPORATION

发明人： Takuro Iwanaga ,  Kazunari Kurita ,  Takeshi Kadono

IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L21/322 ,  H01L29/36

CPC分类号： H01L21/02658 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/3221 ,  H01L29/36

摘要： Provided is a method of manufacturing an epitaxial wafer having an excellent gettering capability while suppressing formation of epitaxial defects. The method includes: a cluster ion irradiation step of irradiating a surface of a silicon wafer having a resistivity of from 0.001 Ω·cm to 0.1 Ω·cm with cluster ions containing at least carbon at a dose of from 2.0×1014/cm2 to 1.0×1016/cm2 to form, on a surface portion of the silicon wafer, a modifying layer composed of a constituent element of the cluster ions in the form of a solid solution; and an epitaxial layer forming step of forming, on the modifying layer on the silicon wafer, an epitaxial layer having a resistivity that is higher than the resistivity of the silicon wafer.