公开(公告)号：US20120322246A1

公开(公告)日：2012-12-20

申请号：US13162813

申请日：2011-06-17

Applicant: Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

Inventor： Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/3205

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/66545

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract translation: 一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的衬底上形成介电层。 在电介质层上形成牺牲栅极层。 对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极叠层。 在第一和第二区域内的栅堆叠内形成ILD层。 去除第一和第二区域中的牺牲栅极层。 在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

公开(公告)号：US20120015493A1

公开(公告)日：2012-01-19

申请号：US13241014

申请日：2011-09-22

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US06380021B1

公开(公告)日：2002-04-30

申请号：US09597193

申请日：2000-06-20

Applicant: Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

Inventor： Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

IPC: H01L218238

CPC classification number: H01L21/823814

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract translation: 描述了一种用于在减少短沟道效应的同时形成PMOSFET的超浅结的新方法。 提供半导体衬底晶片，其中存在至少一个NMOS有源区和至少一个PMOS有效区。 栅电极形成在NMOS和PMOS区域中。 将N型源极/漏极延伸部分注入NMOS区域。 将晶片退火，由此驱动n型源极/漏极延伸部分。此后，在PMOS区域中注入p型源极/漏极延伸部分，其中p型源极/漏极延伸部未经历退火步骤。 间隔件形成在NMOS和PMOS栅电极的侧壁上。 源极/漏极区域被注入NMOS和PMOS区域，其中源极/漏极区域与间隔物自对准以完成集成电路器件的形成。

公开(公告)号：US5281492A

公开(公告)日：1994-01-25

申请号：US54603

申请日：1993-04-29

Applicant: Hsien-Chin Lin

Inventor： Hsien-Chin Lin

IPC: H01M2/04 ,  H01M2/12

CPC classification number: H01M2/1217 ,  H01M2/043

Abstract: A cover device for a storage battery includes a sub-cover that includes a flat bottom with a plurality of first vent-holes, a top portion and a connecting wall which interconnects the flat bottom and the top portion to define a space therein. The cover device further includes a plurality of tubes, each of which having n open end which is connected to each of the first vent-holes of the flat bottom and a closed end which is plugged into a respective inlet-hole of a main cover of the storage battery so as to close the inlet-hole, and a second vent-hole which is formed in the sub-cover and which communicates the space in the sub-cover with an exterior of the same.

Abstract translation: 一种用于蓄电池的盖装置包括：副盖，其包括具有多个第一通气孔的平底部，顶部和连接壁，其将平底部和顶部部分互连以限定其中的空间。 盖装置还包括多个管，每个管具有连接到平底部的每个第一通气孔的n个开口端，并且封闭端被插入主盖的相应入口孔中 所述蓄电池用于封闭所述入口孔;以及第二通气孔，其形成在所述副罩中并将所述副罩中的空间与所述副罩的外部连通。

公开(公告)号：US09312179B2

公开(公告)日：2016-04-12

申请号：US12725554

申请日：2010-03-17

Applicant: Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

公开(公告)号：US08796095B2

公开(公告)日：2014-08-05

申请号：US13241014

申请日：2011-09-22

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US20110227162A1

公开(公告)日：2011-09-22

申请号：US12725554

申请日：2010-03-17

Applicant: Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

Inventor： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

公开(公告)号：US20060014351A1

公开(公告)日：2006-01-19

申请号：US10891577

申请日：2004-07-15

Applicant: Cheng-Yao Lo ,  Hsien-Chin Lin

Inventor： Cheng-Yao Lo ,  Hsien-Chin Lin

IPC: H01L21/4763 ,  H01L21/336 ,  H01L21/44

CPC classification number: H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a low leakage MOS transistor. The transistor includes a gate on a substrate with at least two first spacers adjacent to the gate. A first doped region is formed under each first spacer and a second doped region is formed adjacent to each first doped region, wherein the first doped region and the second doped region are formed in the substrate. A second spacer is formed adjacent to each first spacer. A metal layer is formed on the exposed substrate, the first spacers and the second spacers. The substrate is annealed to form salicide regions on the exposed substrate.

Abstract translation: 一种形成低泄漏MOS晶体管的方法。 晶体管包括在衬底上的栅极，其具有邻近栅极的至少两个第一间隔物。 第一掺杂区域形成在每个第一间隔物下方，并且第二掺杂区域形成为与每个第一掺杂区域相邻，其中第一掺杂区域和第二掺杂区域形成在衬底中。 邻近每个第一间隔件形成第二间隔物。 在暴露的基板，第一间隔件和第二间隔件上形成金属层。 将衬底退火以在暴露的衬底上形成自对准硅化物区域。

公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC: H01L21326

CPC classification number: H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

Abstract translation: 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US06362035B1

公开(公告)日：2002-03-26

申请号：US09498741

申请日：2000-02-07

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

IPC: H01L2144

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  Y10S438/919

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract translation: 描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。 通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。 随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。 在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。 该方法在利用浅沟槽隔离的工艺中示出并且特别有效。