公开(公告)号：US07596662B2

公开(公告)日：2009-09-29

申请号：US11513554

申请日：2006-08-31

Applicant: Srihari Makineni ,  Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Don Newell ,  Li Zhao

Inventor： Srihari Makineni ,  Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Don Newell ,  Li Zhao

IPC: G06F12/00

CPC classification number: G06F12/0897 ,  G06F12/128

Abstract: In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或 在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。 描述和要求保护其他实施例。

公开(公告)号：US20080250415A1

公开(公告)日：2008-10-09

申请号：US11786019

申请日：2007-04-09

Applicant: Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

Inventor： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

IPC: G06F9/46

CPC classification number: G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

公开(公告)号：US20080235487A1

公开(公告)日：2008-09-25

申请号：US11726316

申请日：2007-03-21

Applicant: Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

Inventor： Ramesh Illikkal ,  Hari Kannan ,  Ravishankar Iyer ,  Donald Newell ,  Jaideep Moses ,  Li Zhao

IPC: G06F9/34

CPC classification number: G06F12/126

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有存储位置的翻译后备缓冲器（TLB），每个存储位置包括优先级指示符字段以存储与请求TLB中的数据存储的代理相关联的优先级，以及存储 代理商的标识符，其中TLB根据多个优先级分摊。 描述和要求保护其他实施例。

公开(公告)号：US20070150658A1

公开(公告)日：2007-06-28

申请号：US11319897

申请日：2005-12-28

Applicant: Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Srihari Makineni ,  Donald Newell

Inventor： Jaideep Moses ,  Ravishankar Iyer ,  Ramesh Illikkal ,  Srihari Makineni ,  Donald Newell

IPC: G06F12/00

CPC classification number: G06F12/084 ,  G06F12/126

Abstract: Methods and apparatus to pin a lock in a shared cache are described. In one embodiment, a memory access request is used to pin a lock of one or more cache lines in a shared cache that correspond to the memory access request.

Abstract translation: 描述将锁定在共享高速缓存中的方法和装置。 在一个实施例中，使用存储器访问请求来对应于存储器访问请求的共享高速缓存中的一个或多个高速缓存线的锁定。