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21.发明申请公开(公告)号：US20090019233A1
公开(公告)日：2009-01-15
申请号：US12114788
申请日：2008-05-04
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.
摘要翻译： 提供了一种体现在用于从共享资源到高速缓存代理提供数据线的系统的设计，制造和测试的机器可读存储介质中的设计结构。 该系统提供从缓存代理接收存储在共享资源中的一行数据的请求，将多个相关性状态中的一个分配为数据行的初始一致性状态，多个相关性状态中的每一个可分配 作为数据行的初始相关性状态，并且以分配给数据行的初始一致性状态向高速缓存代理提供数据行。
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公开(公告)号：US20080235456A1
公开(公告)日：2008-09-25
申请号：US11689265
申请日：2007-03-21
申请人： Marcus L. Kornegay , Ngan Pham
发明人： Marcus L. Kornegay , Ngan Pham
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/121
摘要： Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.
摘要翻译： 提供了具有由多个处理器核共享的高速缓存的多核处理环境中的用于共享缓存驱逐的方法和系统。 实施例包括从处理器核心接收在共享高速缓存中加载高速缓存行的请求; 确定共享缓存是否已满; 如果共享高速缓存已满，则确定高速缓存行是否存储在共享高速缓存中，所述高速缓存行已经被共享高速缓存的少于所有处理器核的访问; 并且如果高速缓存行存储在共享高速缓存中的共享高速缓存中的共享高速缓存中的少于所有处理器内核的访问，则驱逐已经被少于所有共享高速缓存的处理器核心访问的高速缓存行。
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23.发明申请公开(公告)号：US20080215818A1
公开(公告)日：2008-09-04
申请号：US12105970
申请日：2008-04-18
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0808
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.
摘要翻译： 可以提供体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构包括对称多处理（SMP）系统。 该系统包括多个节点。 每个节点包括节点控制器和彼此交叉耦合的多个处理器。 该系统还包括耦合到每个节点控制器的至少一个缓存目录，以及耦合到每个节点控制器的无效状态转换逻辑。 无效状态转移逻辑包括能够识别本地节点中的高速缓存行的无效状态转换的程序代码，以驱逐高速缓存行的相应高速缓存目录条目，并将无效状态转换通知转发给节点控制器 为了使家庭节点驱逐高速缓存行的相应高速缓存目录条目，缓存行的主节点。
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公开(公告)号：US08812793B2
公开(公告)日：2014-08-19
申请号：US11425011
申请日：2006-06-19
IPC分类号： G06F12/12
CPC分类号： G06F12/0817
摘要： Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.
摘要翻译： 本发明的实施例解决了有关高速缓存一致性管理的本领域的缺陷，并提供了一种用于在SMP环境中进行无声无效状态转换处理的新颖且非显而易见的方法，系统和装置。 在本发明的一个实施例中，可以提供高速缓存一致性方法。 缓存一致性方法可以包括识别本地节点中的高速缓存线的无效状态转换，驱逐高速缓存行的相应高速缓存目录条目，将无效状态转换通知转发到用于高速缓存线的家庭节点的节点控制器 家庭节点命令驱逐高速缓存行的相应高速缓存目录条目，并将高速缓存行的所有权放弃到主节点。
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公开(公告)号：US07925838B2
公开(公告)日：2011-04-12
申请号：US12137618
申请日：2008-06-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.
摘要翻译： 用于在多处理器系统中维护数据一致性的系统包括具有高速缓存和目录的第一处理器，具有目录的第二处理器，以及具有目录并与第一和第二处理器分离的至少一个附加处理器。 第一处理器被配置为确定在第一处理器的高速缓存中是否没有找到数据线，并将数据线的请求转发到第二处理器。 第二处理器被配置为将数据线从第二处理器转发到第一处理器，更新第二处理器的目录以反映被转发到第一处理器的数据线，并将目录更新消息转发到至少一个附加 处理器来反映被转发到第一处理器的数据线。 目录中的条目包括存储器地址，最近的数据保持器和线路状态。
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26.发明授权Method and system for intelligent and dynamic cache replacement management based on efficient use of cache for individual processor core 失效基于高效使用缓存的单独处理器核心的智能和动态高速缓存替换管理方法和系统公开(公告)号：US07844779B2
公开(公告)日：2010-11-30
申请号：US11955670
申请日：2007-12-13
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/121 , G06F2212/1021
摘要： Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache.
摘要翻译： 确定和应用在计算机处理系统中运行的计算机应用的高速缓存替换策略是通过接收处理器核心数据请求来实现的，该处理器核心数据请求在多个高速缓存行的每条高速缓存线上添加位以识别至少一个处理器的核心ID 核心，它将共享高速缓存中的每个高速缓存行分配给每个处理器核心的标签表，标签表跟踪处理器核心未命中率的索引，以及设置阈值以定义缓存的有用性级别，这取决于是否 或者处理器核心错误率的索引不是超过阈值。 检查阈值和何时不超过阈值，然后应用用于高速缓存替换的共享高速缓存标准策略。 当超过阈值时，来自运行应用程序的处理器核心的高速缓存行从共享高速缓存中逐出。
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27.发明申请SYSTEM AND METHOD FOR DYNAMICALLY SELECTING THE FETCH PATH OF DATA FOR IMPROVING PROCESSOR PERFORMANCE 失效用于动态选择数据路径以提高处理器性能的系统和方法公开(公告)号：US20090037664A1
公开(公告)日：2009-02-05
申请号：US11832803
申请日：2007-08-02
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A system and method for dynamically selecting the data fetch path for improving the performance of the system improves data access latency by dynamically adjusting data fetch paths based on application data fetch characteristics. The application data fetch characteristics are determined through the use of a hit/miss tracker. It reduces data access latency for applications that have a low data reuse rate (streaming audio, video, multimedia, games, etc.) which will improve overall application performance. It is dynamic in a sense that at any point in time when the cache hit rate becomes reasonable (defined parameter), the normal cache lookup operations will resume. The system utilizes a hit/miss tracker which tracks the hits/misses against a cache and, if the miss rate surpasses a prespecified rate or matches an application profile, the hit/miss tracker causes the cache to be bypassed and the data is pulled from main memory or another cache thereby improving overall application performance.
摘要翻译： 用于动态选择用于提高系统性能的数据获取路径的系统和方法通过基于应用数据获取特征动态调整数据获取路径来改善数据访问等待时间。 通过使用命中/未命中跟踪器来确定应用数据提取特性。 它可以降低具有低数据重用率（流音频，视频，多媒体，游戏等）的应用程序的数据访问延迟，从而提高整体应用性能。 在某种意义上说，它是动态的，即在缓存命中率变得合理（定义参数）的任何时候，正常的缓存查找操作将恢复。 该系统利用跟踪高速缓存的命中/未命中的命中/未命中跟踪器，并且如果未命中率超过预定速率或匹配应用程序配置文件，命中/未命中跟踪器将导致高速缓存被绕过并且数据被从 主存储器或另一高速缓存，从而提高整体应用性能。
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公开(公告)号：US07404045B2
公开(公告)日：2008-07-22
申请号：US11322955
申请日：2005-12-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.
摘要翻译： 用于在多处理器系统中维护数据一致性的系统包括具有高速缓存和目录的第一处理器，具有目录的第二处理器，以及具有目录并与第一和第二处理器分离的至少一个附加处理器。 第一处理器被配置为确定在第一处理器的高速缓存中是否没有找到数据线，并将数据线的请求转发到第二处理器。 第二处理器被配置为将数据线从第二处理器转发到第一处理器，更新第二处理器的目录以反映被转发到第一处理器的数据线，并将目录更新消息转发到至少一个附加 处理器来反映被转发到第一处理器的数据线。 目录中的条目包括存储器地址，最近的数据保持器和线路状态。
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