公开(公告)号：US06545338B1

公开(公告)日：2003-04-08

申请号：US09429586

申请日：1999-10-28

Applicant: Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff ,  Milind Weling

Inventor： Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff ,  Milind Weling

IPC: H01L2900

CPC classification number: H01L23/5225 ,  H01L21/76885 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/00

Abstract: A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.

Abstract translation: 提供了一种用于制造具有在半导体晶片上制造的集成CMOS电路和RF电路的半导体器件的方法，以及在半导体晶片上制造的具有集成CMOS电路和RF电路的半导体器件。 该方法包括在下金属化层上形成下金属化层和下电介质层。 金属化线形成在下电介质层上方，在金属化线上方具有上介电层。 然后在上电介质层上形成上金属化层。 完成之后，沿下电介质层，金属化线和上电介质层的侧面形成氧化物间隔物。 最后，在氧化物间隔物之上形成封装的金属化层，使得下金属化层，上金属化层和封装金属化层限定外屏蔽，并且金属化线限定RF线的内导体。

公开(公告)号：US6114246A

公开(公告)日：2000-09-05

申请号：US227034

申请日：1999-01-07

Applicant: Milind Weling

Inventor： Milind Weling

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract translation: 一种在铜化学机械抛光过程中使用抛光止挡膜控制凹陷的方法。 在一个实施例中，该方法包括几个步骤。 一步包括在设置在半导体晶片上的金属层上沉积抛光停止层。 另一步骤是将半导体晶片放置在化学机械抛光机的抛光垫上。 进一步的步骤涉及去除半导体晶片的金属层，并且还优先使用化学机械抛光工艺去除抛光停止层。 抛光停止层的优点是防止沟槽内的金属层的凹陷。 另一步骤是当从半导体晶片的期望区域去除金属层并且半导体晶片基本上是平面时停止化学机械抛光工艺。

公开(公告)号：US5757502A

公开(公告)日：1998-05-26

申请号：US723617

申请日：1996-10-02

Applicant: Milind Weling

Inventor： Milind Weling

IPC: G01B11/06 ,  G01B11/24

CPC classification number: G01B11/24 ,  G01B11/06 ,  Y10S977/852

Abstract: A system for film thickness sample assisted surface profilometry. The sample assisted surface profilometry system of the present invention is utilized to determine an absolute topography variation of a surface of a layer of an integrated circuit with respect to the surface of an underlying layer of known height orientation. The present invention is comprised of a thickness measurement tool for measuring a thickness of the layer at sample points. The thickness measurement tool measures a thickness sample, wherein the thickness sample characterizes the thickness of the layer over the known layer. A surface profilometry tool is coupled to the thickness measurement tool to receive the thickness measurements of the sample points. The surface profilometry tool is utilized to measure relative topography variations of the surface of the layer. The surface profilometry tool then determines absolute height variations of the surface of the layer based on the absolute height reference plane and relative height variations. This information is used to determine a maximum absolute height variation of the topography of the surface of the layer.

Abstract translation: 一种薄膜厚度样品辅助表面轮廓测定系统。 本发明的样品辅助表面轮廓测量系统用于确定集成电路层相对于已知高度方向的下层的表面的绝对形貌变化。 本发明包括用于测量样品点层厚度的厚度测量工具。 厚度测量工具测量厚度样品，其中厚度样品表征已知层上的层的厚度。 表面轮廓测量工具耦合到厚度测量工具以接收采样点的厚度测量。 表面轮廓测量工具用于测量层的表面的相对形貌变化。 然后，表面轮廓测量工具基于绝对高度参考平面和相对高度变化来确定层的表面的绝对高度变化。 该信息用于确定层的表面的形貌的最大绝对高度变化。

公开(公告)号：US5522957A

公开(公告)日：1996-06-04

申请号：US171491

申请日：1993-12-22

Applicant: Milind Weling ,  Calvin T. Gabriel ,  Vivek Jain ,  Dipankar Pramanik

Inventor： Milind Weling ,  Calvin T. Gabriel ,  Vivek Jain ,  Dipankar Pramanik

IPC: H01J37/32 ,  H01L21/306

CPC classification number: H01J37/3244 ,  H01J37/32935 ,  Y10S148/162

Abstract: A method and apparatus for detecting the presence of gaseous impurities, notably oxygen, in a gas mixture that flows over an IC wafer in an etcher during the etching process. The method is based upon the discovery that the ratio of the etch rate of spin-on-glass material to the etch rate of other materials, such as plasma-enhanced chemical vapor deposition (PECVD oxide) materials, varies in a predictable manner with the amount of oxygen contaminating the gas mixture. The standard ratio, in the absence of oxygen, is determined for a given set of processing conditions by first etching an SOG wafer, then etching a PECVD oxide material wafer, measuring the amount of material etched in each case, and from that calculating the respective etch rates, and finally taking the ratio of the two calculated etch rates. This standard ratio is used as the benchmark for future tests. When a production run is to be conducted on a new material, the above procedure is repeated when the equipment is otherwise ready for the run, and the new calculated etch rate ratio is compared with the standard ratio. If they are substantially equal, this indicates a lack of oxygen contamination. If the ratio has changed, and other processing conditions have been taken into account (such as RF power and temperature), this indicates the presence of impurities in the gas mixture, and hence probably a leak in the system, or contamination of the gas source itself. In IC manufacturing, the production run is then typically stopped to correct the problem. Calibration data can be generated in advance to determine by how much to adjust the etching time, given a particular measured ratio that is not the same as the standard ratio. The system may be automatically controlled by a computer that calculates the corrected etching time based upon the measured ratio of the respective etch rates of SOG and the PECVD oxide material.

Abstract translation: 一种用于在蚀刻过程期间在蚀刻器中流过IC晶片的气体混合物中检测气态杂质（特别是氧）的存在的方法和装置。 该方法基于以下发现：旋涂玻璃材料的蚀刻速率与其它材料（诸如等离子体增强化学气相沉积（PECVD氧化物）材料）的蚀刻速率的比率以可预测的方式以 氧气混合物的污染量。 在不存在氧的情况下，通过首先蚀刻SOG晶片，然后蚀刻PECVD氧化物材料晶片，测量在每种情况下蚀刻的材料的量，并从计算相应的 蚀刻速率，最后得到两个计算的蚀刻速率的比值。 该标准比例被用作未来测试的基准。 当对新材料进行生产运行时，当设备准备运行时，重复上述步骤，并将新计算的蚀刻速率比与标准比率进行比较。 如果它们基本相同，则这表明缺乏氧气污染。 如果比例发生变化，并考虑了其他加工条件（如RF功率和温度），则表明气体混合物中存在杂质，因此可能是系统泄漏或气体源的污染 本身。 在IC制造中，通常停止生产运行以纠正问题。 可以预先产生校准数据，以确定调整蚀刻时间的程度，给定与标准比率不同的特定测量比。 该系统可以由计算机自动控制，该计算机基于SOG和PECVD氧化物材料的相应蚀刻速率的测量比来计算校正的蚀刻时间。