公开(公告)号：US20110208989A1

公开(公告)日：2011-08-25

申请号：US12846972

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

IPC: G06F1/08

CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

公开(公告)号：US20110148838A1

公开(公告)日：2011-06-23

申请号：US12640180

申请日：2009-12-17

Applicant: Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

Inventor： Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

IPC: G06F3/038 ,  G05F1/10

CPC classification number: H03K19/018514 ,  H03K19/018528

Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

Abstract translation: 电路包括互补电流模式逻辑驱动器电路和双反馈电流模式逻辑偏置电路。 互补电流模式逻辑驱动器电路提供第一输出电压和第二输出电压。 双反馈电流模式逻辑偏置电路包括第一反馈电路和第二反馈电路。 第一反馈电路响应于第一输出电压为互补电流模式逻辑驱动器电路提供第一偏置电压。 第二反馈电路响应于第二输出电压提供第二偏置电压。