公开(公告)号：US20240361799A1

公开(公告)日：2024-10-31

申请号：US18635817

申请日：2024-04-15

申请人： Rambus Inc.

发明人： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC分类号： G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H04L7/00 ,  H04L7/10

CPC分类号： G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/00

摘要： A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US12130759B2

公开(公告)日：2024-10-29

申请号：US18138667

申请日：2023-04-24

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Holden Jessup

IPC分类号： G06F13/16

CPC分类号： G06F13/1689

摘要： The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US12130758B2

公开(公告)日：2024-10-29

申请号：US17821935

申请日：2022-08-24

申请人： QUALCOMM Incorporated

发明人： Tomer Shoshani ,  Albert Yosher ,  Yaron Shachar

IPC分类号： G06F13/16 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/1689 ,  G06F13/4068

摘要： Systems and methods for data transmission power optimization are disclosed. In one aspect, the system consolidates signals from multiple narrowband channels in a radio frequency (RF) integrated circuit (IC) (RFIC) into a single shared buffer and evenly distributes packets based on the signals across lanes in a communication bus to a modem circuit. Such even utilization of the lanes of the bus allows for idle periods to occur on the bus, during which a low power or sleep state may be used to reduce power consumption.

公开(公告)号：US20240354594A1

公开(公告)日：2024-10-24

申请号：US18671756

申请日：2024-05-22

申请人： Deep Vision Inc.

发明人： Raju Datla ,  Mohamed Shahim ,  Suresh Kumar Vennam ,  Sreenivas Aerra Reddy

IPC分类号： G06N3/10 ,  G06F13/16 ,  G06F13/28 ,  G06N3/04 ,  G06N3/08

CPC分类号： G06N3/10 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  G06N3/04 ,  G06N3/08

摘要： A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

公开(公告)号：US20240345972A1

公开(公告)日：2024-10-17

申请号：US18647048

申请日：2024-04-26

申请人： Infineon Technologies LLC

发明人： Clifford Zitlaw ,  Stephan Rosner ,  Hans Van Antwerpen ,  Morgan Andrew Whately

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/1689 ,  G06F13/28 ,  G06F13/409 ,  G06F13/4291

摘要： A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

公开(公告)号：US20240323113A1

公开(公告)日：2024-09-26

申请号：US18677994

申请日：2024-05-30

申请人： Hewlett Packard Enterprise Development LP

发明人： Jonathan P. Beecroft ,  Abdulla M. Bataineh ,  Thomas L. Court

IPC分类号： H04L45/28 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/28 ,  H04L69/40

CPC分类号： H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/6235 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

摘要： Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic with fast, effective flow control of individual applications and traffic flows in conjunction with an end host. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. As a result, an ingress edge switch can perform fine grain flow control of individual sources of the flows residing on an end host.

公开(公告)号：US20240311330A1

公开(公告)日：2024-09-19

申请号：US18399463

申请日：2023-12-28

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Narasimha Lanka ,  Peter Onufryk ,  Swadesh Choudhary ,  Gerald Pasdast ,  Zuoguo Wu ,  Dimitrios Ziakas ,  Sridhar Muthrasanallur

IPC分类号： G06F13/42 ,  G06F13/16

CPC分类号： G06F13/4295 ,  G06F13/1689 ,  G06F2213/0038 ,  G06F2213/0064

摘要： Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

公开(公告)号：US20240311021A1

公开(公告)日：2024-09-19

申请号：US18610888

申请日：2024-03-20

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406

CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

摘要： A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

公开(公告)号：US12093195B2

公开(公告)日：2024-09-17

申请号：US18134920

申请日：2023-04-14

申请人： Intel Corporation

发明人： Christopher P. Mozak ,  Steven T. Taylor ,  Alvin Shing Chye Goh

IPC分类号： G06F12/00 ,  G06F9/30 ,  G06F13/16 ,  G06F13/42 ,  G06F18/214 ,  G11C7/10 ,  G11C7/22 ,  H03M13/09

CPC分类号： G06F13/1689 ,  G06F9/30029 ,  G06F13/4243 ,  G06F18/214 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/222 ,  H03M13/09

摘要： Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

公开(公告)号：US20240296129A1

公开(公告)日：2024-09-05

申请号：US18659407

申请日：2024-05-09

申请人： Texas Instruments Incorporated

发明人： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC分类号： G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/603 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

摘要： A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.