公开(公告)号：US20090307691A1

公开(公告)日：2009-12-10

申请号：US12132650

申请日：2008-06-04

Applicant: Thomas Moscibroda ,  Onur Mutlu

Inventor： Thomas Moscibroda ,  Onur Mutlu

IPC: G06F9/46

CPC classification number: G06F13/1652 ,  Y02D10/14

Abstract: Systems and methods that coordinate operations among a plurality of memory controllers to make a decision for performing an action based in part on state information. A control component facilitates exchange of information among memory controllers, wherein exchanged state information of the memory controllers are further employed to perform computations that facilitate the decision making process.

Abstract translation: 协调多个存储器控制器之间的操作以部分地基于状态信息执行动作的决定的系统和方法。 控制部件促进存储器控制器之间的信息交换，其中进一步使用存储器控制器的交换状态信息来执行便于决策过程的计算。

公开(公告)号：US20090055580A1

公开(公告)日：2009-02-26

申请号：US11842772

申请日：2007-08-21

Applicant: Thomas Moscibroda ,  Onur Mutlu

Inventor： Thomas Moscibroda ,  Onur Mutlu

IPC: G06F12/00

CPC classification number: G06F13/1642

Abstract: Providing for multi-tiered RAM control is provided herein. As an example, a RAM access management system can include multiple input controllers each having a request buffer and request scheduler. Furthermore, a request buffer associated with a controller can vary in size with respect to other buffers. Additionally, request schedulers can vary in complexity and can be optimized at least for a particular request buffer size. As a further example, a first controller can have a large memory buffer and simple scheduling algorithm optimized for scalability. A second controller can have a small memory buffer and a complex scheduler, optimized for efficiency and high RAM performance. Generally, RAM management systems described herein can increase memory system scalability for multi-core parallel processing devices while providing an efficient and high bandwidth RAM interface.

Abstract translation: 本文提供了多层RAM控制。 作为示例，RAM访问管理系统可以包括每个具有请求缓冲器和请求调度器的多个输入控制器。 此外，与控制器相关联的请求缓冲器的大小可以相对于其他缓冲器而变化。 此外，请求调度器可以在复杂性方面变化，并且可以至少针对特定请求缓冲器大小进行优化。 作为另一示例，第一控制器可以具有大的存储器缓冲器和针对可扩展性优化的简单调度算法。 第二个控制器可以有一个小的内存缓冲区和一个复杂的调度器，为效率和高性能而优化。 通常，本文描述的RAM管理系统可以提供多核并行处理设备的存储器系统可扩展性，同时提供高效且高带宽的RAM接口。

公开(公告)号：US20090031314A1

公开(公告)日：2009-01-29

申请号：US11782719

申请日：2007-07-25

Applicant: Thomas Moscibroda ,  Onur Mutlu

Inventor： Thomas Moscibroda ,  Onur Mutlu

IPC: G06F9/46 ,  G06F12/00

CPC classification number: G06F9/52

Abstract: Architecture for a multi-threaded system that applies fairness to thread memory request scheduling such that access to the shared memory is fair among different threads and applications. A fairness scheduling algorithm provides fair memory access to different threads in multi-core systems, thereby avoiding unfair treatment of individual threads, thread starvation, and performance loss caused by a memory performance hog (MPH) application. The thread slowdown is determined by considering the thread's inherent memory-access characteristics, computed as the ratio of the real latency that the thread experiences and the latency (ideal latency) that the thread would have experienced if it had run as the only thread in the same system. The highest and lowest slowdown values are then used to generate an unfairness parameter which when compared to a threshold value provides a measure of fairness/unfairness currently occurring in the request scheduling process. The architecture provides a balance between fairness and throughput.

Abstract translation: 多线程系统的架构，适用于线程内存请求调度的公平性，使得对不同线程和应用程序之间共享内存的访问是公平的。 公平调度算法提供了对多核系统中不同线程的公平存储器访问，从而避免了由内存性能猪（MPH）应用引起的各个线程的不公平的处理，线程饥饿和性能损失。 线程减速是通过考虑线程的固有内存访问特性来确定的，计算方法是线程经历的实际延迟与线程所经历的延迟（理想延迟）的比例，如果它作为唯一的线程运行 相同的系统 然后，最高和最低的减速值用于产生不公平参数，当与阈值相比时，提供了在请求调度过程中当前发生的公平/不公平的度量。 该架构在公平性和吞吐量之间取得了平衡。