利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

1171 records (took 0.026 seconds)

    Memory controller with pseudo-channel support
    2.
    发明授权
    Memory controller with pseudo-channel support 有权

    公开(公告)号：US12117945B2

    公开(公告)日：2024-10-15

    申请号：US17849117

    申请日：2022-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Hideki Kanayama ,  YuBin Yao

    IPC: G06F13/16

    CPC classification number: G06F13/1689 ,  G06F13/1621 ,  G06F13/1642

    Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

    STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF
    3.
    发明公开
    STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240296131A1

    公开(公告)日：2024-09-05

    申请号：US18662097

    申请日：2024-05-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangmuk HWANG ,  Jaegeun PARK ,  Hojun SHIM ,  Byungchul YOO

    IPC: G06F13/16 ,  G06F13/28

    CPC classification number: G06F13/1642 ,  G06F13/161 ,  G06F13/1689 ,  G06F13/28

    Abstract: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

    Scatter and Gather Streaming Data through a Circular FIFO
    5.
    发明公开
    Scatter and Gather Streaming Data through a Circular FIFO 审中-公开

    公开(公告)号：US20240264963A1

    公开(公告)日：2024-08-08

    申请号：US18637305

    申请日：2024-04-16

    Applicant: Apple Inc.

    Inventor： Marc A. Schaub ,  Roy G. Moss

    IPC: G06F13/37 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54 ,  G06F13/16 ,  G06F13/28

    CPC classification number: G06F13/37 ,  G06F9/30069 ,  G06F9/5022 ,  G06F9/544 ,  G06F13/1642 ,  G06F13/28

    Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.

    Out-of-order buffer and associated management method
    7.
    发明授权
    Out-of-order buffer and associated management method 有权

    公开(公告)号：US12056049B2

    公开(公告)日：2024-08-06

    申请号：US17989729

    申请日：2022-11-18

    Applicant: RDC Semiconductor Co., Ltd.

    Inventor： Jyun-Yan Li ,  Po-Hsiang Huang ,  Ya-Ting Chen ,  Yao-An Tsai ,  Shu-Wei Yi

    IPC: G06F13/16 ,  G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F13/1642 ,  G06F2212/60

    Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

    SELECTIVE DISTRIBUTION OF TRANSLATION ENTRY INVALIDATION REQUESTS IN A MULTITHREADED DATA PROCESSING SYSTEM
    10.
    发明公开
    SELECTIVE DISTRIBUTION OF TRANSLATION ENTRY INVALIDATION REQUESTS IN A MULTITHREADED DATA PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20240220418A1

    公开(公告)日：2024-07-04

    申请号：US18091679

    申请日：2022-12-30

    Applicant: International Business Machines Corporation

    Inventor： Derek E. WILLIAMS ,  Florian Auernhammer

    IPC: G06F12/1045 ,  G06F12/0831 ,  G06F13/16

    CPC classification number: G06F12/1045 ,  G06F12/0833 ,  G06F13/1642

    Abstract: A data processing system includes a master and multiple snoopers communicatively coupled to a system fabric for communicating requests, where the master and snoopers are distributed among a plurality of nodes. The data processing system maintains logical partition (LPAR) information for each of a plurality of LPARs, wherein the LPAR information indicates, for each of the plurality of LPARs, which of the plurality of nodes includes at least one snooper among the plurality of snoopers that holds an address translation entry for that LPAR. Based on the LPAR information, the master selects a broadcast scope of a multicast request on the system fabric, where the broadcast scope includes fewer than all of the plurality of nodes. The master repetitively issues, on the system fabric, the multicast request utilizing the selected broadcast scope until the multicast request is successfully received by all of the plurality of snoopers within the broadcast scope.

Patent Agency Ranking