公开(公告)号：US07146482B2

公开(公告)日：2006-12-05

申请号：US10723506

申请日：2003-11-25

Applicant: David F. Craddock ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Donald W. Schmidt

Inventor： David F. Craddock ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Donald W. Schmidt

IPC: G06F9/26

CPC classification number: G06F9/30003 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/342

Abstract: A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

Abstract translation: 一种将存储器映射的输入输出操作管理到备用地址空间的方法，包括：执行指向与第一适配器相关联的机器的第一存储器映射输入输出备用地址空间的第一指令，以将与第一适配器相关联的资源分配给 过程按照az / Architecture的定义; 其中所选择的过程将所述机器的问题状态中执行的加载和存储指令中的至少一个发出到所选择的资源的所选地址位置。 该方法还包括确保所选择的资源对应于所分配的资源，并确定所选择的进程与分配资源的进程相对应。

公开(公告)号：US07058837B2

公开(公告)日：2006-06-06

申请号：US10435970

申请日：2003-05-12

Applicant: David A. Elko ,  Richard K. Errickson ,  Steven N. Goss ,  Dan F. Greiner ,  Carol B. Hernandez ,  Ronald M. Smith, Sr. ,  David H. Surman

Inventor： David A. Elko ,  Richard K. Errickson ,  Steven N. Goss ,  Dan F. Greiner ,  Carol B. Hernandez ,  Ronald M. Smith, Sr. ,  David H. Surman

IPC: G06F15/16 ,  G06F1/04 ,  G06F1/12 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L7/04

CPC classification number: G06F9/546

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message. Sending the response includes marking the response with a second departure time-stamp responsive to the receiver system clock if the delay variable is equal to zero and transmitting the response to the sender system. The response is received at the sender system. Receiving the response includes delaying the processing of the response if the delay variable is equal to zero until the time on the sender system clock is greater than the second departure time-stamp and recording a time associated with the delaying the processing of the response in the delay variable.

Abstract translation: 公开了一种提供消息时间排序设施的方法。 该方法包括在发送者系统处发起消息的消息定时器排序设施。 启动包括将延迟变量设置为零。 响应于启动消息时间排序设施，该消息被发送到接收机系统。 发送消息包括响应于发送者系统时钟的第一起始时间戳来标记消息并将消息发送到接收机系统。 消息在接收机系统处被接收，接收包括延迟消息的处理，直到接收机系统时钟的时间大于第一个出发时间戳，并且记录与将消息的处理延迟相关联的时间 延迟变量。 响应于接收到该消息，对该消息的响应被发送到发送者系统。 发送响应包括响应于接收机系统时钟的第二个出发时间戳来标记响应，如果延迟变量等于零并将响应发送到发送器系统。 发送方系统收到响应。 如果延迟变量等于0，则接收响应包括延迟响应的处理，直到发送方系统时钟的时间大于第二个出发时间戳，并记录与延迟处理响应相关的时间 延迟变量。

公开(公告)号：US08793699B2

公开(公告)日：2014-07-29

申请号：US12051628

申请日：2008-03-19

Applicant: Richard K. Errickson ,  Geoffrey A. Crew ,  Welela Haileselaissie ,  Robert M. Whalen, Jr.

Inventor： Richard K. Errickson ,  Geoffrey A. Crew ,  Welela Haileselaissie ,  Robert M. Whalen, Jr.

IPC: G06F9/46 ,  G06F9/54

CPC classification number: G06F9/546 ,  G06F2209/548

Abstract: A computer program product, apparatus and method for negating initiative for select entries from a shared, strictly FIFO initiative queue in a multi-tasking multi-processor environment. An exemplary embodiment includes a computer program product for negating initiative for select entries from a shared initiative queue in a multi-tasking multi-processor environment, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including identifying an element within the environment that has failed and recovered, not removing the element from the shared initiative queue and entering a boundary element entry into the shared initiative queue.

Abstract translation: 一种计算机程序产品，装置和方法，用于在多任务多处理器环境中从共享的严格FIFO主动队列中取消选择条目的主动性。 一个示例性实施例包括一种计算机程序产品，用于在多任务多处理器环境中从共享主动队列中拒绝主动选择条目的计算机程序产品，该计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由 处理电路，用于执行包括识别环境中已经失败和恢复的元素的方法，而不是从共享主动队列中移除元素并且将边界元素条目输入到共享主动队列中。

公开(公告)号：US08762125B2

公开(公告)日：2014-06-24

申请号：US12036986

申请日：2008-02-25

Applicant: Richard K. Errickson ,  Thomas A. Gregg ,  John S. Houston ,  Ambrose A. Verdibello, Jr.

Inventor： Richard K. Errickson ,  Thomas A. Gregg ,  John S. Houston ,  Ambrose A. Verdibello, Jr.

IPC: G06F9/455 ,  G06F13/10 ,  G06F9/54 ,  H04L12/56

CPC classification number: G06F13/105 ,  G06F9/544 ,  G06F9/546 ,  H04L49/901

Abstract: A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers.

Abstract translation: 一种用于在多任务多处理器环境中模拟信道的计算机程序产品，装置和方法，包括识别具有用于多个物理信道中的每一个的相关联的物理信道标识符的多个物理信道，将来自多个 用于生成多个仿真信道，多个仿真信道中的每一个具有虚拟信道标识符，在通信链路上映射多个仿真信道，从而生成仿真信道路径 对于多个仿真信道中的每一个，为每个仿真信道的多个队列对链路缓冲器定义队列对链路缓冲器，并增加队列对链路缓冲器的数量。

公开(公告)号：US07895462B2

公开(公告)日：2011-02-22

申请号：US12051631

申请日：2008-03-19

Applicant: Richard K. Errickson ,  Leonard W. Helmer, Jr. ,  John S. Houston

Inventor： Richard K. Errickson ,  Leonard W. Helmer, Jr. ,  John S. Houston

IPC: G06F11/00

CPC classification number: G06F9/546 ,  G06F2209/548

Abstract: A computer program product, apparatus and method for managing recovery and control of a communications link via out-of-band signaling. An exemplary embodiment includes sending a command, sending an invalidate request to a buffer associated with the command and receiving a response to the invalidate request at least one of prior to the command reaching the recipient and after the command reaching the recipient.

Abstract translation: 一种用于通过带外信令管理通信链路的恢复和控制的计算机程序产品，装置和方法。 示例性实施例包括发送命令，向与命令相关联的缓冲器发送无效请求，并且在到达接收者的命令之前以及在到达接收者的命令之后至少接收到对无效请求的响应。

公开(公告)号：US07668207B2

公开(公告)日：2010-02-23

申请号：US11873557

申请日：2007-10-17

Applicant: David F. Craddock ,  Richard K. Errickson ,  Thomas A. Gregg ,  Bruce Marshall Walk

Inventor： David F. Craddock ,  Richard K. Errickson ,  Thomas A. Gregg ,  Bruce Marshall Walk

IPC: H04J3/06

CPC classification number: G06F1/14 ,  G04G5/00 ,  G04G7/00

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract translation: 提供了分别在第一和第二计算机上同步第一和第二时钟的系统，方法和制品。 第一和第二计算机具有分别具有第三和第四时钟的第一和第二网络接口卡。 系统利用由第三和第四时钟产生的时间戳值来同步第一和第二时钟时钟。

公开(公告)号：US20090217238A1

公开(公告)日：2009-08-27

申请号：US12058034

申请日：2008-03-28

Applicant: Richard K. Errickson ,  Leonard W. Helmer, JR. ,  John S. Houston ,  R. Timothy Tomaselli ,  Ambrose A. Verdibello, JR.

Inventor： Richard K. Errickson ,  Leonard W. Helmer, JR. ,  John S. Houston ,  R. Timothy Tomaselli ,  Ambrose A. Verdibello, JR.

IPC: G06F9/44

CPC classification number: G06F9/546 ,  G06F2209/548

Abstract: A computer program product for incorporating state machine controls into existing non-state machine environments includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining a state machine representation for an existing environment, assigning state indicators to each state of the state machine, transcoding existing software flags of the environment into modifier values associated with the state indicators, assigning state values based on the modifier values and the state indicators, assigning event identifiers for transitions from the state values, and creating a tabular representation of the determined state machine, the tabular representation providing next state information based on the event identifiers and the state values.

Abstract translation: 用于将状态机控制结合到现有非状态机器环境中的计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括确定现有环境的状态机表示，将状态指示符分配给状态机的每个状态，将现有环境的软件标志转码为与状态指示符相关联的修改值，基于修改值分配状态值，以及 状态指示符，从状态值分配用于转换的事件标识符，以及创建所确定的状态机的表格表示，表格表示基于事件标识符和状态值来提供下一状态信息。

公开(公告)号：US20090217007A1

公开(公告)日：2009-08-27

申请号：US12036979

申请日：2008-02-25

Applicant: Richard K. Errickson ,  Welela Haileselaissie ,  Leonard W. Helmer, JR. ,  John S. Houston ,  An Zhu

Inventor： Richard K. Errickson ,  Welela Haileselaissie ,  Leonard W. Helmer, JR. ,  John S. Houston ,  An Zhu

IPC: G06F9/30

CPC classification number: G06F9/54

Abstract: A computer program product, apparatus and method for identifying processors in a multi-tasking multiprocessor network, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including storing a service record for a port to which an LID has been assigned, retrieving service records for nodes to which channel paths may connect, retrieving path records that provide address destinations for the nodes identified in the service records, initiating channel initialization for the channel paths defined for the port and removing the service record for the port.

Abstract translation: 一种用于识别多任务多处理器网络中的处理器的计算机程序产品，装置和方法，所述计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由所述处理电路执行以执行包括存储服务 针对已经分配了LID的端口的记录，检索通道路径可以连接到的节点的服务记录，检索为服务记录中标识的节点提供地址目的地的路径记录，为为 端口并删除端口的服务记录。

公开(公告)号：US20090216518A1

公开(公告)日：2009-08-27

申请号：US12036986

申请日：2008-02-25

Applicant: Richard K. Errickson ,  Thomas A. Gregg ,  John S. Houston ,  Ambrose A. Verdibello, JR.

Inventor： Richard K. Errickson ,  Thomas A. Gregg ,  John S. Houston ,  Ambrose A. Verdibello, JR.

IPC: G06F9/455

CPC classification number: G06F13/105 ,  G06F9/544 ,  G06F9/546 ,  H04L49/901

Abstract: A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers.

Abstract translation: 一种用于在多任务多处理器环境中模拟信道的计算机程序产品，装置和方法，包括识别具有用于多个物理信道中的每一个的相关联的物理信道标识符的多个物理信道，将来自多个 用于生成多个仿真信道，多个仿真信道中的每一个具有虚拟信道标识符，在通信链路上映射多个仿真信道，从而生成仿真信道路径 对于多个仿真信道中的每一个，为每个仿真信道的多个队列对链路缓冲器定义队列对链路缓冲器，并增加队列对链路缓冲器的数量。

公开(公告)号：US07552436B2

公开(公告)日：2009-06-23

申请号：US10723405

申请日：2003-11-25

Applicant: Frank William Brice, Jr. ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Damian L. Osisek ,  Donald W. Schmidt

Inventor： Frank William Brice, Jr. ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Damian L. Osisek ,  Donald W. Schmidt

IPC: G06F9/46 ,  G06F3/00

CPC classification number: G06F12/0292 ,  G06F9/45537 ,  G06F2212/206

Abstract: A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.

Abstract translation: 一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出交替地址空间的第二指令，以根据z / Architecture的定义加载数据; 将与所述第一替代地址空间相关联的实际资源和虚拟资源中的至少一个分配给进程; 确保所选择的进程与分配资源的进程相对应。 该过程发生第一指令和第二指令中的至少一个，从而导致使用第一替代地址空间执行存储和加载中的至少一个。