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    Load page table entry address instruction execution based on an address translation format control field
    1.
    发明授权
    Load page table entry address instruction execution based on an address translation format control field 有权
    基于地址转换格式控制字段加载页表项目地址指令执行

    公开(公告)号：US08930673B2

    公开(公告)日：2015-01-06

    申请号：US14065796

    申请日：2013-10-29

    申请人： Dan F Greiner ,  Lisa C Heller ,  Damian L Osisek ,  Erwin F Pfeffer ,  Timothy J Slegel

    发明人： Dan F Greiner ,  Lisa C Heller ,  Damian L Osisek ,  Erwin F Pfeffer ,  Timothy J Slegel ,  Gustav E Sittmann

    IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个分段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    Dynamic address translation with translation exception qualifier
    2.
    发明授权
    Dynamic address translation with translation exception qualifier 有权
    动态地址转换与翻译异常限定符

    公开(公告)号：US08683176B2

    公开(公告)日：2014-03-25

    申请号：US13312079

    申请日：2011-12-06

    申请人： Dan F Greiner ,  Lisa C Heller ,  Damian L Osisek ,  Erwin Pfeffer

    发明人： Dan F Greiner ,  Lisa C Heller ,  Damian L Osisek ,  Erwin Pfeffer

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    Interruption facility for adjunct processor queues
    5.
    发明授权
    Interruption facility for adjunct processor queues 有权
    辅助处理器队列的中断设施

    公开(公告)号：US08316172B2

    公开(公告)日：2012-11-20

    申请号：US13196986

    申请日：2011-08-03

    申请人： Charles W. Gainey, Jr. ,  Klaus Meissner ,  Damian L. Osisek ,  Klaus Werner

    发明人： Charles W. Gainey, Jr. ,  Klaus Meissner ,  Damian L. Osisek ,  Klaus Werner

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

    摘要翻译： 辅助处理器队列的中断设施。 响应于队列从无应答等待状态转移到回复挂起状态，发起中断。 该中断向处理器通知对请求的响应在队列上等待。 为了使队列利用中断能力，它可以被中断。

    VIRTUALIZATION OF STORAGE BUFFERS USED BY ASYNCHRONOUS PROCESSES
    7.
    发明申请
    VIRTUALIZATION OF STORAGE BUFFERS USED BY ASYNCHRONOUS PROCESSES 有权
    存储缓冲区的虚拟化由异步过程使用

    公开(公告)号：US20120198453A1

    公开(公告)日：2012-08-02

    申请号：US13446862

    申请日：2012-04-13

    申请人： Damian L. Osisek ,  Donald W. Schmidt ,  Phil C. Yeh

    发明人： Damian L. Osisek ,  Donald W. Schmidt ,  Phil C. Yeh

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

    摘要： The amount of host real storage provided to a large guest storage buffer is controlled. This control is transparent to the guest that owns the buffer and is executing an asynchronous process to update the buffer. The control uses one or more indicators to determine when additional host real storage is to be provided.

    摘要翻译： 控制提供给大客户机存储缓冲区的主机实际存储量。 该控件对拥有缓冲区的客户端是透明的，并正在执行异步进程来更新缓冲区。 该控制使用一个或多个指示器来确定何时需要提供附加的主机实际存储。

    Dynamic Address Translation With Translation Exception Qualifier
    9.
    发明申请
    Dynamic Address Translation With Translation Exception Qualifier 有权
    动态地址转换与翻译异常限定符

    公开(公告)号：US20120084488A1

    公开(公告)日：2012-04-05

    申请号：US13312079

    申请日：2011-12-06

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。