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公开(公告)号：US20210281497A1
公开(公告)日：2021-09-09
申请号：US17182914
申请日：2021-02-23
Applicant: STMicroelectronics Application GMBH
Inventor： Fred Rennig
IPC: H04L12/26
Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.
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22.发明授权公开(公告)号：US11032067B2
公开(公告)日：2021-06-08
申请号：US16022110
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
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公开(公告)号：US10949570B2
公开(公告)日：2021-03-16
申请号：US16039103
申请日：2018-07-18
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
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公开(公告)号：US20200348890A1
公开(公告)日：2020-11-05
申请号：US16932426
申请日：2020-07-17
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.
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公开(公告)号：US20200341836A1
公开(公告)日：2020-10-29
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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Patent Agency Ranking
公开(公告)号：US20200169459A1
公开(公告)日：2020-05-28
申请号：US16679796
申请日：2019-11-11
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
IPC: H04L12/24 , H03K19/177 , H04L29/06 , H04L29/08
Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.
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公开(公告)号：US20200167220A1
公开(公告)日：2020-05-28
申请号：US16693103
申请日：2019-11-22
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
IPC: G06F11/07
Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.
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公开(公告)号：US20190294572A1
公开(公告)日：2019-09-26
申请号：US16360229
申请日：2019-03-21
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20190007201A1
公开(公告)日：2019-01-03
申请号：US16022033
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
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公开(公告)号：US20180357012A1
公开(公告)日：2018-12-13
申请号：US16002534
申请日：2018-06-07
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F9/30
Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.
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