公开(公告)号：US09454378B2

公开(公告)日：2016-09-27

申请号：US14083010

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

IPC: G06F3/00 ,  G06F13/00 ,  G06F9/44 ,  G06F3/06 ,  G06F9/445

CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。

公开(公告)号：US09218639B2

公开(公告)日：2015-12-22

申请号：US14039820

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： Guy Cote ,  Mark P. Rygh ,  Timothy John Millet ,  Jim C. Chou ,  Joseph J. Cheng

IPC: G06T15/00 ,  G06T1/20 ,  H04N19/61 ,  H04N19/423 ,  H04N19/436

CPC classification number: G06T1/20 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

Abstract: A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm.

Abstract translation: 一种用于块处理管线的骑士订单处理方法，其中从管线的下一个块输入下一个块，并且在该帧中从左侧获取一个或多个列。 骑士的订单方法可以在管道中的相邻块之间提供间隔，以便于数据从下游阶段到上游阶段的反馈。 输入帧中的块行可以被划分为限制骑士命令方法以维持相邻块数据的位置的行的集合。 无效的块可以被输入到第一组行的左侧和最后一组行的右侧的流水线，并且这些行的集合可以被视为水平排列而不是垂直排列，以保持连续性 的骑士秩序算法。

公开(公告)号：US20150095630A1

公开(公告)日：2015-04-02

申请号：US14083010

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。