公开(公告)号：US20180260335A1

公开(公告)日：2018-09-13

申请号：US15452989

申请日：2017-03-08

Applicant: ARM Limited

Inventor： John Michael HORLEY ,  Dan BROOK

IPC: G06F12/1009 ,  G06F12/1036

CPC classification number: G06F12/1009 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

Abstract: Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.

公开(公告)号：US20140237300A1

公开(公告)日：2014-08-21

申请号：US13769992

申请日：2013-02-19

Applicant: ARM LIMITED

Inventor： John Michael HORLEY

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F11/3476 ,  G06F11/3636

Abstract: A data processing apparatus has processing circuitry for executing program instructions and trace circuitry for generating trace data indicating processing activities of the processing circuitry. The trace circuitry may detect a lockup state of the processing circuitry in which the processing circuitry does not make forward progress of execution of the program instructions. In response to detecting the lockup state, the trace circuitry may include in the trace data a lockup identifier indicating that the lockup state has occurred.

Abstract translation: 数据处理装置具有用于执行程序指令和跟踪电路的处理电路，用于产生指示处理电路的处理活动的跟踪数据。 跟踪电路可以检测处理电路的锁定状态，其中处理电路不会执行程序指令的执行进度。 响应于检测到锁定状态，跟踪电路可以在跟踪数据中包括指示发生锁定状态的锁定标识符。

公开(公告)号：US20140195786A1

公开(公告)日：2014-07-10

申请号：US14205438

申请日：2014-03-12

Applicant: ARM Limited

Inventor： Paul Anthony GILKERSON ,  John Michael HORLEY

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/865 ,  G06F2201/88

Abstract: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry.

Abstract translation: 一种跟踪单元，用于生成指示执行指令流的处理器的处理活动的跟踪数据项，该单元包括用于监视处理器的行为的跟踪电路; 用于存储用于控制跟踪电路的当前跟踪控制数据的存储电路; 用于存储至少一些跟踪控制数据的数据存储器; 所述跟踪电路被配置为响应于所述指令组的执行的检测而将所述跟踪控制数据存储在所述数据存储器中，其中所述跟踪电路响应于检测所述至少一个处理器取消至少一组所述推测执行的指令 检索存储在数据存储器中的跟踪控制数据的一部分，用于在取消的推测性执行的指令之前执行的指令组，并将所检索的跟踪控制数据存储在存储电路中。

公开(公告)号：US20130339686A1

公开(公告)日：2013-12-19

申请号：US13968991

申请日：2013-08-16

Applicant: ARM Limited

Inventor： John Michael HORLEY ,  Simon John CRASKE ,  Michael John GIBBS ,  Paul Anthony GILKERSON

IPC: G06F9/30

CPC classification number: G06F11/3495 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30145 ,  G06F11/348

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

Abstract translation: 处理电路响应于至少一个条件指令，以根据至少一个条件标志的子集的当前值执行条件操作。 提供跟踪电路用于产生指示由处理电路执行的操作的跟踪数据元素。 当处理电路4处理至少一个所选择的指令时，跟踪电路产生跟踪数据元素，跟踪数据元素包括至少指示确定条件指令的结果所需的条件标志的子集的跟踪条件值。 相应的诊断装置使用跟踪条件值来确定至少一个条件指令的处理结果。