公开(公告)号：US20190068172A1

公开(公告)日：2019-02-28

申请号：US15683962

申请日：2017-08-23

Applicant: ARM LIMITED

Inventor： Ashley John CRAWFORD ,  John Michael HORLEY

IPC: H03J7/06 ,  H03K21/40 ,  G06F1/32 ,  H03B5/12 ,  G07C3/04 ,  H03K9/06

Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

公开(公告)号：US20180260227A1

公开(公告)日：2018-09-13

申请号：US15555239

申请日：2016-02-11

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  John Michael HORLEY ,  Stephan DIESTELHORST ,  Richard Roy GRISENTHWAITE

IPC: G06F9/38 ,  G06F11/30 ,  G06F11/34

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

公开(公告)号：US20170026255A1

公开(公告)日：2017-01-26

申请号：US15191950

申请日：2016-06-24

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Christopher Vincent SEVERINO

IPC: H04L12/26

CPC classification number: H04L43/04 ,  H04L43/12

Abstract: A system, apparatus and method for gathering monitoring data relating to the operation of a data processing system are disclosed. The data processing system comprises a monitor controller and a plurality of monitors which gather monitoring data relating to the operation of the data processing system. Each monitor does not send its monitoring data to the monitor controller unsolicited, but merely indicates to the monitor controller that it has such data ready for transmission. In response to reception of a data ready signal from more than one monitor, the monitor controller selects one of these monitors and sends it a data transmission command, thereby avoiding resource contention in a shared resource between data transmissions from more than one monitor.

Abstract translation: 公开了一种用于收集与数据处理系统的操作相关的监控数据的系统，装置和方法。 数据处理系统包括监视器控制器和收集与数据处理系统的操作有关的监视数据的多个监视器。 每个监视器不会将其监视数据发送到监视器控制器，而是仅向监视器控制器指示其具有准备传输的数据。 响应于来自多个监视器的数据就绪信号的接收，监视器控制器选择这些监视器中的一个并向其发送数据传输命令，从而避免来自多于一个监视器的数据传输之间的共享资源中的资源争用。

公开(公告)号：US20160246543A1

公开(公告)日：2016-08-25

申请号：US15008569

申请日：2016-01-28

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  John Michael HORLEY

IPC: G06F3/06

CPC classification number: G06F11/3636

Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.

Abstract translation: 提供了一种用于生成跟踪流的装置，用于产生跟踪流的方法，用于接收跟踪流的装置和接收跟踪流的方法。 跟踪流中的报头项目和有效负载项目分别分组在一起，连续的报头项目序列和有效载荷项目的连续序列。 这可以例如促进跟踪流的生成，其中跟踪流被对准到预定长度（例如，对应于其中要存储跟踪流的存储器的对准），因此有助于其解释。

公开(公告)号：US20150254160A1

公开(公告)日：2015-09-10

申请号：US14633630

申请日：2015-02-27

Applicant: ARM Limited

Inventor： John Michael HORLEY

IPC: G06F11/34

CPC classification number: G06F11/3476 ,  G06F11/3065 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/88

Abstract: An apparatus for processing data is disclosed in which the operations of data processing circuitry are monitored by one or more trace data sources which generate items of trace data indicative of the data processing operations performed by the data processing circuitry. Trace data source identifiers in a resulting trace stream indicate the source of items of trace data and a selected trace data source identifier is included in the trace stream in response to a received flush request signal. All items of trace data generated before the apparatus received the flush request signal are included in the trace stream before the selected trace data source identifier, such that the conclusion of the response of the apparatus to the flush request signal can be identified.

Abstract translation: 公开了一种用于处理数据的装置，其中数据处理电路的操作由一个或多个跟踪数据源监视，该跟踪数据源产生指示由数据处理电路执行的数据处理操作的跟踪数据项。 产生的跟踪流中的跟踪数据源标识符指示跟踪数据的项目的来源，并且响应于接收到的刷新请求信号，所选跟踪数据源标识符被包括在跟踪流中。 在设备接收到刷新请求信号之前生成的所有跟踪数据项目都包括在所选择的跟踪数据源标识符之前的跟踪流中，使得能够识别装置对刷新请求信号的响应的结论。

公开(公告)号：US20140281433A1

公开(公告)日：2014-09-18

申请号：US13795611

申请日：2013-03-12

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Simon John CRASKE

IPC: G06F11/34

CPC classification number: G06F11/0766 ,  G06F11/0721

Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.

Abstract translation: 数据处理装置包括用于执行指令流的处理电路和用于从一个或多个异常中选择要由处理电路处理的异常的异常处理电路。 未选择的异常被称为挂起的异常。 数据处理装置还包括跟踪生成电路，其根据处理电路的活动产生跟踪数据分组。 跟踪产生电路检测待处理的异常，并且如果检测到异常待处理，则在至少一个跟踪数据分组中包括挂起异常的指示。 通过跟踪特定异常何时进行，而不是当它被选择用于由处理电路处理时，可以更准确地确定何时发生异常，而不是最终处理何时。

公开(公告)号：US20140229771A1

公开(公告)日：2014-08-14

申请号：US14185121

申请日：2014-02-20

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Paul Anthony GILKERSON ,  Michael John GIBBS

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/3024 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/364 ,  G06F11/3664

Abstract: A data processing apparatus is provided with trace circuitry for generating a plurality of trace streams including an instruction trace stream 10 and a data trace stream 12. The instruction elements within the instruction trace stream and the data elements within the data trace stream are marked with key values KV such that a match may be made between data elements and corresponding instruction elements. When predetermined conditions are met, synchronisation markers 66 are inserted in both the instruction trace stream 10 and the data trace stream 12 in order to permit a precise correlation to be made between the instruction elements and the data elements when the data is subsequently analysed.

Abstract translation: 数据处理装置具有跟踪电路，用于产生包括指令跟踪流10和数据跟踪流12的多个跟踪流。指令跟踪流内的指令元素和数据跟踪流内的数据元素用键标记 值KV，使得可以在数据元素和对应的指令元素之间进行匹配。 当满足预定条件时，同步标记66插入指令跟踪流10和数据跟踪流12两者中，以便在随后分析数据时允许在指令元素和数据元素之间进行精确的相关。

公开(公告)号：US20230088780A1

公开(公告)日：2023-03-23

申请号：US17999167

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Michael John WILLIAMS ,  Alasdair GRANT ,  John Michael HORLEY

IPC: G06F9/34 ,  G06F9/26 ,  G06F9/38

Abstract: Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.

公开(公告)号：US20210034503A1

公开(公告)日：2021-02-04

申请号：US16971415

申请日：2019-01-17

Applicant: Arm Limited

Inventor： Michael John WILLIAMS ,  Graeme Peter BARNES ,  John Michael HORLEY

IPC: G06F11/36

Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items. The number of metadata items accessed by each instance of the metadata access operation is non-deterministic by the debugger from the metadata access operation. However, the at least one command is such that the plurality of instances of the metadata access operation are performed by the processing circuitry without the debugger interrogating the processing circuitry between each instance of the metadata access operation to determine progress in the number of metadata items accessed. Such an approach can significantly improve the efficiency of performing such accesses to metadata items under debugger control.

公开(公告)号：US20190179642A1

公开(公告)日：2019-06-13

申请号：US16309620

申请日：2016-09-13

Applicant: ARM LIMITED

Inventor： Michael John GIBBS ,  John Michael HORLEY

IPC: G06F9/38 ,  G06F11/34 ,  G06F9/32 ,  G06F11/36

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of predetermined instructions within the sequence. The instruction sequence includes at least one branch-future instruction that effectively turns an instruction identified by the branch-future instruction into a branch, and in particular causes the processing circuitry to branch to a target address identified by the branch-future instruction when that identified instruction is encountered within the instruction sequence. A branch control cache is used to store branch control information derived from the branch-future instruction, and the trace generation circuitry is arranged to detect, based on that branch control information, when the identified instruction has been encountered by the processing circuitry, and upon such detection to then issue within the trace stream a trace element to indicate that a branch to the target address has occurred. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch-future instructions.