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公开(公告)号：US20220019642A1
公开(公告)日：2022-01-20
申请号：US16930650
申请日：2020-07-16
Applicant: Arm Limited
Inventor： Simon John CRASKE
Abstract: An apparatus has a multiplier array for implementing a multiply-accumulate operation. The multiplier array has a plurality of rows, where each row comprises multiplexer circuitry and adder circuitry, the multiplexer circuitry selecting, in dependence on a control input, one of a first multiplexer input value and a second multiplexer input value to provide as a first adder input value to the adder circuitry. In each row other than an initial row, the adder circuitry also receives as a second adder input value at least a portion of a result value produced in a preceding row. The mode of operation can be changed between a multiplication mode where the multiplier array implements the multiply-accumulate operation and a linear interpolation mode where the multiplier array implements a linear interpolation operation between a lower limit value and an upper limit value based on a weighting value. When in the multiplication mode, each row of the multiplier array has its multiplexer circuitry controlled by an associated bit of a multiplicand value, whilst the first multiplexer input is set to zero and the second multiplexer input is set to a multiplier value. When in the linear interpolation mode, each row of the multiplier array has its multiplexer circuitry controlled by an associated bit of the weighting value, with the lower limit value and upper limit value being provided as inputs to the multiplexer circuitry.
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公开(公告)号：US20210157601A1
公开(公告)日：2021-05-27
申请号：US16695745
申请日：2019-11-26
Applicant: Arm Limited
Inventor： Simon John CRASKE
Abstract: Exception control circuitry controls exception handling for processing circuitry. In response to an initial exception occurring when the processing circuitry is in a given exception level, the initial exception to be handled in a target exception level, the exception control circuitry stores exception control information to at least one exception control register associated with the target exception level, indicating at least one property of the initial exception or of processor state at a time the initial exception occurred. When at least one exception intercept configuration parameter stored in a configuration register indicates that exception interception is enabled, after storing the exception control information, and before the processing circuitry starts processing an exception handler for handling the initial exception in the target exception level, the exception control circuitry triggers a further exception to be handled in a predetermined exception level.
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公开(公告)号：US20190095209A1
公开(公告)日：2019-03-28
申请号：US16080736
申请日：2017-03-21
Applicant: ARM LIMITED
Inventor： Alasdair GRANT , Thomas Christopher GROCUTT , Simon John CRASKE
CPC classification number: G06F9/30065 , G06F9/30036 , G06F9/30145 , G06F9/325 , G06F9/3842
Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.
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4.发明申请公开(公告)号：US20180196746A1
公开(公告)日：2018-07-12
申请号：US15741830
申请日：2016-06-14
Applicant: ARM LIMITED
Inventor： Simon John CRASKE
IPC: G06F12/06
CPC classification number: G06F12/06 , G06F9/3013 , G06F9/34 , G06F9/35 , G06F9/3861 , G06F12/1441 , G06F2212/1008
Abstract: An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating an allowable range of addresses for the pointer (62). Processing circuitry (4) performs, in response to a first type of instruction (70) identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information (64) associated with the pointer stored in the given bounded pointer storage element (60).
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公开(公告)号：US20180173535A1
公开(公告)日：2018-06-21
申请号：US15578477
申请日：2016-03-31
Applicant: ARM LIMITED
Inventor： Max John BATLEY , Simon John CRASKE , Ian Michael CAULFIELD , Peter Richard GREENHALGH , Allan John SKILLMAN , Antony John PENTON
CPC classification number: G06F9/3885 , G06F9/30189 , G06F9/3802 , G06F9/3804 , G06F9/383 , G06F9/3851
Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behaviour to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).
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Patent Agency Ranking
公开(公告)号：US20160371501A1
公开(公告)日：2016-12-22
申请号：US15189284
申请日：2016-06-22
Applicant: ARM LIMITED
Inventor： John Michael HORLEY , Michael John WILLIAMS , Simon John CRASKE , Uma Maheswari RAMALINGAM
IPC: G06F21/62
CPC classification number: G06F21/74
Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.
Abstract translation: 数据处理装置包括具有相关联的存储器存储器和一个或多个寄存器的处理元件，处理元件被配置为以两个或更多个安全模式执行处理活动，以便禁止在一个安全模式中执行的处理活动以访问 至少一些与另一个安全模式中执行的处理活动相关联的信息; 其中处理元件被配置为响应于使分支从第一安全模式中的处理活动转移到第二安全模式中的处理活动的功能调用，以将一个或多个寄存器的内容存储在存储器中 并且响应于分支返回到第一安全模式，从存储器存储器检索寄存器内容; 以及跟踪装置，被配置为生成指示所述处理元件的处理活动的跟踪数据项; 其中所述跟踪装置被配置为检测所述处理元件的分支返回操作并且生成与所述分支返回操作有关的一个或多个跟踪数据项; 并且其中所述跟踪装置被配置为响应于到所述第一安全模式的分支返回而检测所述处理元件从所述存储器存储器检索寄存器内容，并且生成与所述寄存器内容的检索相关的跟踪数据的一个或多个其它项目 从内存存储。
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公开(公告)号：US20160210465A1
公开(公告)日：2016-07-21
申请号：US14912300
申请日：2014-07-15
Applicant: ARM LIMITED
Inventor： Simon John CRASKE , Antony John PENTON
CPC classification number: G06F21/629 , G06F9/30043 , G06F9/45558 , G06F9/468 , G06F9/4812 , G06F13/24 , G06F21/00 , G06F21/50 , G06F21/60 , G06F2009/45579
Abstract: A data processing apparatus (2) has processing circuitry (4) for executing first software (12) at a first privilege level EL1 and second software (10) at a second privilege level EL2 higher than the first privilege level. Attributes may be set by the first and second software (10, 12) to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software (10) specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software (12) specifies that the execution of the instruction cannot be interrupted.
Abstract translation: 数据处理装置（2）具有处理电路（4），用于以第一特权级别EL1执行第一软件（12），第二软件（10）处于高于第一权限级别的第二权限级别EL2。 属性可以由第一和第二软件（10,12）设置，以指示是否可以中断数据访问指令的执行。 对于由第二软件（10）设置的第二属性指定可以中断指令的预定类型的数据访问指令，即使由第一软件（12）设置的第一属性指定 指令的执行不能中断。
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公开(公告)号：US20230367554A1
公开(公告)日：2023-11-16
申请号：US17743880
申请日：2022-05-13
Applicant: Arm Limited
Inventor： Simon John CRASKE
IPC: G06F7/72
CPC classification number: G06F7/727
Abstract: There is provided a method and an apparatus for calculating an output modulo k value of an input data value. The apparatus is provided with input data value analysis circuitry to consider the input data value as a plurality of partial operands, and to determine a plurality of modulo k values corresponding to the plurality of partial operands. The apparatus is provided with modulo k calculation circuitry comprising plural combination stages to replace one or more groups of input modulo k values with one or more combined modulo k values. The plural combination stages comprise a first combination stage to receive the plurality of modulo k values as inputs and to output an intermediate reduced plurality of modulo k values, and one or more further combination stages to sequentially combine one or more groups of the intermediate reduced plurality of modulo k values to generate the output modulo k value.
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公开(公告)号：US20200184199A1
公开(公告)日：2020-06-11
申请号：US16213814
申请日：2018-12-07
Applicant: Apical Ltd , Arm Limited
Inventor： Daren CROXFORD , Simon John CRASKE
Abstract: Examples of the present disclosure relate to methods for controlling a display device. In one such example, data representing a result of an eyewear detection operation is obtained. Dependent on the obtained data, a control signal is outputted to adjust a display parameter of the display device. Performing the eyewear detection operation comprises receiving image data representing a user of the display device, and processing the image data using object recognition to determine whether or not the user is wearing eyewear of a predetermined type.
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公开(公告)号：US20190079770A1
公开(公告)日：2019-03-14
申请号：US16085053
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Thomas Christopher GROCUTT , Richard Roy GRISENTHWAITE , Simon John CRASKE , François Christopher Jacques BOTMAN , Bradley John SMITH
CPC classification number: G06F9/3806 , G06F9/3005 , G06F9/30054 , G06F9/30145 , G06F9/321 , G06F9/322 , G06F9/34
Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.
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