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公开(公告)号：US20190166158A1
公开(公告)日：2019-05-30
申请号：US15825524
申请日：2017-11-29
Applicant: Arm Limited
Inventor： Thomas Christopher GROCUTT , Yasuo ISHII
IPC: H04L29/06
CPC classification number: H04L63/1441 , G06F9/3844 , G06F9/3861 , G06F21/53 , G06F21/78 , H04L63/1416
Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.
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22.发明申请公开(公告)号：US20190163601A1
公开(公告)日：2019-05-30
申请号：US16321503
申请日：2017-08-10
Applicant: ARM LIMITED
Inventor： François Christopher Jacques BOTMAN , Thomas Christopher GROCUTT , John Michael HORLEY , Michael John WILLIAMS
Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being
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公开(公告)号：US20190095209A1
公开(公告)日：2019-03-28
申请号：US16080736
申请日：2017-03-21
Applicant: ARM LIMITED
Inventor： Alasdair GRANT , Thomas Christopher GROCUTT , Simon John CRASKE
CPC classification number: G06F9/30065 , G06F9/30036 , G06F9/30145 , G06F9/325 , G06F9/3842
Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.
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公开(公告)号：US20190056933A1
公开(公告)日：2019-02-21
申请号：US16078780
申请日：2017-03-17
Applicant: ARM LIMITED
Inventor： Thomas Christopher GROCUTT
Abstract: Processing circuitry (4) performs multiple beats of processing in response to a vector instruction, each beat comprising processing corresponding to a portion of a vector value comprising multiple data elements. The processing circuitry (4) sets beat status information (22) indicating which beats of a group of two or more vector instructions have completed. In response to a return-from-event request indicating a return to processing of the given vector instruction, the processing circuitry (4) resumes processing of the group of uncompleted vector instructions while suppressing beats already completed, based on the beat status information (22).
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公开(公告)号：US20230010863A1
公开(公告)日：2023-01-12
申请号：US17757197
申请日：2020-11-05
Applicant: Arm Limited
Inventor： Thomas Christopher GROCUTT
Abstract: Processing circuitry has a handler mode and a thread mode. In response to an exception condition, a switch to handler mode is made. In response to an intermodal calling branch instruction specifying a branch target address when the processing circuitry is in the handler mode, an instruction decoder controls the processing circuitry to save a function return address to a function return address storage location; switch a current mode of the processing circuitry to the thread mode; and branch to an instruction identified by the branch target address. This can be useful for deprivileging of exceptions.
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Patent Agency Ranking
公开(公告)号：US20220366037A1
公开(公告)日：2022-11-17
申请号：US17756949
申请日：2020-11-11
Applicant: Arm Limited
Inventor： Thomas Christopher GROCUTT
Abstract: A processing circuitry having a secure domain and a less secure domain. A control storage location stores a domain transition disable configuration parameter specifying whether domain transitions between the secure domain and the less secure domain are enabled or disabled in at least one mode of the process-ing circuitry. In the at least one mode of the processing circuitry, when the domain transition disable configuration parameter specifies that said domain transitions are disabled in said at least one mode, a disabled domain transition fault is signalled in response to an attempt to transition between domains in either direction. This can help support lazy configuration of resources for the secure domain or less secure domain for a thread expected only to need the other domain.
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公开(公告)号：US20220156301A1
公开(公告)日：2022-05-19
申请号：US17098815
申请日：2020-11-16
Applicant: Arm Limited
IPC: G06F16/35 , G06F16/335
Abstract: Data processing apparatuses, methods and computer programs are disclosed. A range definition register is arranged to store a range specifier and filtering operations are performed with respect to a specified transaction by reference to the range definition register. The range definition register stores the range specifier in a format comprising a significand and an exponent, wherein a range of data identifiers is at least partially defined by the range specifier. When the specified transaction is with respect to a data identifier within the range of data identifiers, the filtering operations performed are dependent on attribute data associated with the range of data identifiers.
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公开(公告)号：US20210326134A1
公开(公告)日：2021-10-21
申请号：US17271373
申请日：2019-08-20
Applicant: Arm Limited
Inventor： Thomas Christopher GROCUTT
Abstract: An apparatus comprises: an instruction decoder to decode instructions; processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space. In response to a range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder controls the processing circuitry 4 to set, in at least one software-accessible storage location; a status value indicative of whether the first address and the second address correspond to the same memory attribute entry.
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公开(公告)号：US20200167160A1
公开(公告)日：2020-05-28
申请号：US16628418
申请日：2018-06-19
Applicant: ARM LIMITED
Abstract: A data processing system includes processing circuitry for executing context-data-dependent-program instructions which are decoded by decoder circuitry. Such context-data-dependent program instructions perform processing which are dependent upon currently existing context data. As an example, the context-data-dependent program instructions may be floating point instructions and the context data may be rounding mode information. The decoder circuitry supports a context save instruction which saves context data when it is marked as having been used and saves default context data when the current context data is marked as not having been used. The decoder circuitry further supports a context restore instruction which restores context data when the current context data is marked as having been used and permits the current context data to continue for future use when it is marked as currently unused.
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公开(公告)号：US20190339971A1
公开(公告)日：2019-11-07
申请号：US16314936
申请日：2017-06-06
Applicant: ARM LIMITED
Inventor： Thomas Christopher GROCUTT
Abstract: An apparatus and method are provided for performing a vector rearrangement operation as data elements are moved between memory and vector registers. The apparatus has processing circuitry for performing operations specified by a sequence of program instructions, and a set of vector registers, where each vector register is arranged to store a vector comprising a plurality of data elements. The processing circuitry includes access circuitry to move the data elements between memory and multiple vector registers of the set, and to perform a rearrangement operation as the data elements are moved so that the data elements are arranged in a first organisation in the memory and are arranged in a second, different, organisation in the vector registers. Decode circuitry is arranged to be responsive to a group of rearrangement instructions within the sequence of program instructions to produce control signals to control execution of each rearrangement instruction by the processing circuitry. Each rearrangement instruction in the group defines a data element access pattern that differs to the data element access pattern defined by each other rearrangement instruction in the group, and that causes the access circuitry to access more than one vector register amongst the multiple vector registers involved in the rearrangement operation. Through such an approach, the access circuitry performs the rearrangement operation as a result of the processing circuitry executing all of the rearrangement instructions in the group. The use of such a group of rearrangement instructions can enable an efficient performance of the rearrangement operation by reducing stalling within the apparatus that might otherwise occur if all of the required steps to be performed to implement the rearrangement operation were implemented in response to execution of a single instruction.
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