公开(公告)号：US20200335458A1

公开(公告)日：2020-10-22

申请号：US16388829

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01Q1/22 ,  H01Q9/16

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer, a first package body, a first antenna and an electronic component. The circuit layer has a first surface and a second surface opposite to the first surface. The first package body is disposed on the first surface of the circuit layer. The first antenna penetrates the first package body and is electrically connected to the circuit layer. The electronic component is disposed on the second surface of the circuit layer.

公开(公告)号：US20200035654A1

公开(公告)日：2020-01-30

申请号：US16518837

申请日：2019-07-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Cheng-Yuan KUNG

IPC: H01L25/10 ,  H01L41/047 ,  H01L41/053 ,  H01L23/522 ,  H01L41/23 ,  H01L41/25 ,  H03H9/60 ,  H03H9/64

Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.

公开(公告)号：US20190181082A1

公开(公告)日：2019-06-13

申请号：US16277962

申请日：2019-02-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH ,  Cheng-Yuan KUNG

IPC: H01L23/498 ,  H05K1/16 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L2224/11 ,  H05K1/162

Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.

公开(公告)号：US20190067261A1

公开(公告)日：2019-02-28

申请号：US15691014

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE ,  Chien-Hua CHEN

IPC: H01L27/01 ,  H01L49/02 ,  H01L21/683

Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.