公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

Abstract: A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US12119319B2

公开(公告)日：2024-10-15

申请号：US17549810

申请日：2021-12-13

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Ki Yeul Yang ,  Eun Taek Jeong ,  Du Young Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: In one example, an electronic device includes a substrate, which has a dielectric structure includes a dielectric structure top side and a dielectric structure bottom side opposite to the dielectric structure top side, and a conductive structure comprising a protruded via that extends from the dielectric structure bottom side. An electronic component is coupled to the conductive structure at the dielectric structure top side, and a terminal is coupled to the protruded via such that the protruded via extends into the terminal. Other examples and related methods are also disclosed herein.

公开(公告)号：US12119293B2

公开(公告)日：2024-10-15

申请号：US17497261

申请日：2021-10-08

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Shinji Maekawa ,  Hiroshi Kudo ,  Takamasa Takano ,  Hiroshi Mawatari ,  Masaaki Asano

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/15 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838 ,  H05K3/46 ,  H01L23/49894 ,  H01L2221/68345

Abstract: A through electrode substrate includes a substrate provided with a through hole, a through electrode positioned in the through hole, and a first wiring structure including at least a first wiring layer positioned on a first surface of the substrate, and a second wiring layer positioned on the first wiring layer. The first wiring layer and the second wiring layer respectively have an insulation layer and an electroconductive layer. A first insulation layer of the first wiring layer includes at least an organic layer. At least one wiring layer of the first wiring structure includes an inorganic layer having insulation properties, the inorganic layer being positioned to a first side of the organic layer of the first insulation layer of the first wiring layer.

公开(公告)号：US12119291B2

公开(公告)日：2024-10-15

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/32 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49894 ,  H01L2224/08225 ,  H01L2224/32225

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US12119235B2

公开(公告)日：2024-10-15

申请号：US17245856

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Sih-Hao Liao

IPC: H01L21/48 ,  G03F7/00 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L21/4857 ,  G03F7/70 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/25 ,  H01L27/14634 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2924/14335 ,  H01L2924/1461

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

公开(公告)号：US20240339389A1

公开(公告)日：2024-10-10

申请号：US18276907

申请日：2022-02-15

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Satoru KURAMOCHI

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49894

Abstract: A through-electrode substrate including a through-electrode adapted for high density and miniaturization and capable of reducing a transmission loss at a high frequency is provided.
A through-electrode substrate according to the present disclosure includes a substrate having a first face and a second face opposite to the first face and having a through-hole extending from the first face to the second face, and a through-electrode located in the through-hole of the substrate. A hole diameter of the through-hole varies according to a position in a thickness direction of the substrate. The through-hole has a minimum diameter part having a minimum hole diameter of greater than or equal to 10 μm. A maximum hole diameter of the through-hole is less than or equal to 60 μm. The through-electrode has an adhesion layer and a conductive layer in order from a side face of the through-hole toward a center of the through-hole. A dielectric loss tangent of the substrate at a frequency of 20 GHz is greater than or equal to 0.0003 and less than or equal to 0.0005.

公开(公告)号：US20240339388A1

公开(公告)日：2024-10-10

申请号：US18626736

申请日：2024-04-04

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Jun SAKAI ,  Shiho SHIMADA

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894

Abstract: A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part including an insulating layer and a conductor layer. The minimum wiring width of wirings in the conductor layer of the first build-up part is smaller than the minimum wiring width of wirings in the conductor layer of the second build-up part. The minimum inter-wiring distance of the wirings in the first part is smaller than the minimum inter-wiring distance of the wirings in the second part. The first build-up part is formed such that the conductor layer includes a conductor pattern including a first metal layer, a second metal layer, and a third metal layer. The width of the first metal layer is larger than the width of the second metal layer. The width of the third metal layer is larger than the width of the first metal layer.

公开(公告)号：US20240332231A1

公开(公告)日：2024-10-03

申请号：US18194591

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/3135 ,  H01L23/49894 ,  H01L25/0652 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2924/182

Abstract: Direct bond interconnect in topographic packages and methods of making. The topographic packages include a first die hybrid bonded to a substrate, the first die located in a first device level. A second die located in a second device level above the first device, the second die hybrid bonded to the first die. The topographic packages also include a third die located in a third device level above the second die, the third die hybrid bonded to a top surface of the second device level.

公开(公告)号：US20240321762A1

公开(公告)日：2024-09-26

申请号：US18678813

申请日：2024-05-30

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H05K1/141 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20240312897A1

公开(公告)日：2024-09-19

申请号：US18576841

申请日：2022-07-07

Applicant: ACT IDENTITY TECHNOLOGY LIMITED

Inventor： Gang Chen

IPC: H01L23/498 ,  H01L21/52

CPC classification number: H01L23/49855 ,  H01L21/52 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/49894

Abstract: A chip module (40a, 40b, 62) is disclosed as including an integrated-circuit (IC) chip (34, 64), a first flexible substrate layer (18) with a number of holes (28), a second adhesive substrate layer (16) with a number of holes (26), and a third substrate layer (14) made of an electrically conductive material, the second substrate layer being sandwiched between and fixedly engaged with the first and third substrate layers, the holes of the first substrate layer and the holes of the second substrate layer being aligned with each other to form a number of cavities (12, 66) each receiving at least a part of the IC chip.