摘要:
This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed.Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed.A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.
摘要:
A disk array controller is made up of multiple disk array control units for implementing the data read/write operation and each having channel IF units, disk IF units, cache memory units and shared memory units. The disk array controller further includes inter connections for interconnecting the shared memory units and interconnecting the cache memory units across the border of disk array control units. Thereby alleviating the deterioration of performance due to the data transfer between the disk array control units, when the multiple disk array control units are to be operated as a single disk array controller.
摘要:
A disk array controller, comprising a channel interface unit for connecting a host computer through a first type channel; a channel interface unit for connecting a host computer through a second type channel; a plurality of disk interface units provided with an interface with a magnetic disk unit respectively; a cache memory unit; and a shared memory unit; wherein the number of access paths connected to said cache memory unit is less than the number of access paths connected to said shared memory unit.
摘要:
A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.
摘要:
A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.
摘要:
A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an interface with a magnetic disk unit respectively, a cache memory unit, and a shared memory unit. The number of access paths connected to said cache memory unit is less than the number of access paths connected to the shared memory unit.
摘要:
A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.
摘要:
A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.
摘要:
A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.
摘要:
This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed.Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed.A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.