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    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES
    1.
    发明公开
    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES 审中-公开

    公开(公告)号：US20240354012A1

    公开(公告)日：2024-10-24

    申请号：US18760849

    申请日：2024-07-01

    Applicant: Ambiq Micro, Inc.

    Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    Storage devices and methods of operating storage devices
    3.
    发明授权
    Storage devices and methods of operating storage devices 有权

    公开(公告)号：US12079493B2

    公开(公告)日：2024-09-03

    申请号：US17850723

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wonjong Song ,  Soonyoung Kim ,  Taeyoung Kim

    IPC: G06F3/06

    CPC classification number: G06F3/0626 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A storage device includes a nonvolatile memory device and a storage controller. The nonvolatile memory device includes a first memory region having a first write speed and a second memory region having a second write speed different from the first write speed. The storage controller includes an internal buffer and stores data from an external host in the first memory region by priority in a first mode. The storage controller controls a data migration operation by performing a read operation-transfer operation to read a second data that is pre-stored in the first memory region by a first unit and to transfer the first unit of data to a data input/output (I/O) circuit of the nonvolatile memory device a plurality of times and by storing the second data transferred to the data I/O circuit in the second memory region.

    Non-volatile memory with reduced word line switch area
    4.
    发明授权
    Non-volatile memory with reduced word line switch area 有权

    公开(公告)号：US12032837B2

    公开(公告)日：2024-07-09

    申请号：US17957424

    申请日：2022-09-30

    Applicant: SanDisk Technologies LLC

    Inventor： Yuki Mizutani ,  Kazutaka Yoshizawa ,  Kiyokazu Shishido ,  Eiichi Fujikura

    IPC: G06F3/06

    CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

    Multi-domain configurable data compressor/de-compressor
    5.
    发明授权
    Multi-domain configurable data compressor/de-compressor 有权

    公开(公告)号：US11966597B1

    公开(公告)日：2024-04-23

    申请号：US17936765

    申请日：2022-09-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Dmitri Pavlichin ,  Shubham Chandak ,  Itschak Weissman ,  Christopher George Burgess

    IPC: G06F3/06

    CPC classification number: G06F3/0626 ,  G06F3/0631 ,  G06F3/0673

    Abstract: A data service implements a configurable data compressor/decompressor using a recipe generated for a particular data set type and using compression operators of a common registry (e.g., pantry) that are referenced by the recipe, wherein the recipe indicates at which nodes of a compression graph respective ones of the compression operators of the registry are to be implemented. The configurable data compressor/decompressor provides a customizable framework for compressing data sets of different types (e.g., belonging to different data domains) using a common compressor/decompressor implemented using a common set of compression operators.

    Processing-in-memory control method for efficient instruction processing and computing device applying same
    7.
    发明授权
    Processing-in-memory control method for efficient instruction processing and computing device applying same 有权

    公开(公告)号：US11907578B2

    公开(公告)日：2024-02-20

    申请号：US17587239

    申请日：2022-01-28

    Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

    Inventor： Young Kyu Kim ,  Byung Soo Kim ,  Young Jong Jang

    IPC: G06F3/06 ,  G06F9/30

    CPC classification number: G06F3/0659 ,  G06F3/0626 ,  G06F3/0673 ,  G06F9/30043

    Abstract: The present disclosure relates to a method for classifying instructions according to the number of operands required for processing-in-memory instruction processing, and a computing device applying same. Efficient instruction processing in a processing-in-memory may include identifying the number of operands required when processing an instruction queuing to be processed, interpreting the instruction queuing to be processed and processing an instruction corresponding to the identified number of required operands. When the number of required operands is 0, the instruction interpretation may interpret the instruction queuing to be processed as a WRITE instruction, and the instruction processing may execute memory writing. When the number of required operands is not 0, the instruction processing may execute memory reading in an internal memory of the processing-in-memory by the same number of times as the number of operands required in the instruction interpreted in the instruction interpretation.

    Data processing system and data compression method
    9.
    发明授权
    Data processing system and data compression method 有权

    公开(公告)号：US11842055B2

    公开(公告)日：2023-12-12

    申请号：US17642843

    申请日：2021-03-04

    Applicant: Hitachi, Ltd.

    Inventor： Takahiro Naruko ,  Hiroaki Akutsu ,  Akifumi Suzuki ,  Katsuto Sato

    IPC: G06F3/06

    CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0673

    Abstract: Provided is a data processing system which includes a processor and a storage device, and inputs/outputs data using a learned compander that compresses and expands data, wherein the data processing system comprises an estimation unit which uses learning data and estimates a region of interest to a data model, and a learning unit which causes the compander to learn according to an evaluation function in which each region was weighted based on the region of interest, and a result of the compander compressing and expanding the learning data.

    Solid state disk, data transmitting method and intermediary controller to support reduced SSD controller pad count
    10.
    发明授权
    Solid state disk, data transmitting method and intermediary controller to support reduced SSD controller pad count 有权

    公开(公告)号：US11809746B2

    公开(公告)日：2023-11-07

    申请号：US17541306

    申请日：2021-12-03

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuan-Chieh Wang ,  Shih-Chou Juan ,  Nai-Ping Kuo

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

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