Virtual world event notification from a persistent world game server in a logically partitioned game console
    21.
    发明申请
    Virtual world event notification from a persistent world game server in a logically partitioned game console 审中-公开
    虚拟世界事件通知从持久的世界游戏服务器在一个逻辑分区的游戏机

    公开(公告)号:US20080090659A1

    公开(公告)日:2008-04-17

    申请号:US11548904

    申请日:2006-10-12

    IPC分类号: A63F9/24

    摘要: A mechanism is provided for generating event notifications for offline characters from within a persistent world online game. A player agent for an offline player runs in a secondary partition in a video game console while a primary application runs in a main partition. The offline player agent includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent composes an event notification message and presents the message to the offline player through speech or through an interface within the primary application. Event notification messages may include images, voice (text-to-speech), sound, or video.

    摘要翻译: 提供了一种用于从永久性世界在线游戏内产生离线角色的事件通知的机制。 主要应用程序在主分区中运行时,用于离线播放器的播放器代理在视频游戏控制台的辅助分区中运行。 离线播放器代理包括事件监视器,其监视由游戏服务器维护的持久虚拟世界中发生的事件。 当触发离线播放器规则的游戏事件发生时,播放器代理构成事件通知消息,并通过语音或通过主应用程序中的界面将消息呈现给离线播放器。 事件通知消息可以包括图像,语音(文本到语音),声音或视频。

    Dynamically rewriting branch instructions in response to cache line eviction
    22.
    发明授权
    Dynamically rewriting branch instructions in response to cache line eviction 有权
    动态地重写分支指令以响应缓存线驱逐

    公开(公告)号:US08782381B2

    公开(公告)日:2014-07-15

    申请号:US13444890

    申请日:2012-04-12

    IPC分类号: G06F9/44

    摘要: Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

    摘要翻译: 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分,直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令,其直接或间接地对目标当前高速缓存行中的代码部分。 此外,重写一个或多个重写的分支指令,以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

    Dynamically rewriting branch instructions to directly target an instruction cache location
    23.
    发明授权
    Dynamically rewriting branch instructions to directly target an instruction cache location 有权
    动态地重写分支指令直接指向指令高速缓存位置

    公开(公告)号:US08627051B2

    公开(公告)日:2014-01-07

    申请号:US13442919

    申请日:2012-04-10

    IPC分类号: G06F9/44

    CPC分类号: G06F9/3806 G06F12/0875

    摘要: Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

    摘要翻译: 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外,响应于确定目标指令存在于指令高速缓存中,机制直接将代码部分的执行分支到指令高速缓存中的目标指令,而不需要来自指令高速缓存运行时系统的干预。 此外,响应于确定目标指令不能被确定为存在于指令高速缓存中,这些机制将代码部分的执行重定向到指令高速缓存运行时系统。

    Arranging Binary Code Based on Call Graph Partitioning
    24.
    发明申请
    Arranging Binary Code Based on Call Graph Partitioning 有权
    基于调用图划分二进制代码

    公开(公告)号:US20110321021A1

    公开(公告)日:2011-12-29

    申请号:US12823244

    申请日:2010-06-25

    IPC分类号: G06F9/45

    CPC分类号: G06F8/4442

    摘要: Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

    摘要翻译: 提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。 这些机制产生一部分代码的调用图。 调用图中的节点和边被加权以生成加权调用图。 然后根据权重,调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图,使得与一个或多个节点的子集相关联的二进制代码 调用图被组合到基于分区的各个高速缓存行。 然后输出与划分的调用图对应的二进制代码,以在计算设备中执行。

    Rewriting Branch Instructions Using Branch Stubs
    25.
    发明申请
    Rewriting Branch Instructions Using Branch Stubs 有权
    使用分支存根重写分支指令

    公开(公告)号:US20110321002A1

    公开(公告)日:2011-12-29

    申请号:US12823204

    申请日:2010-06-25

    IPC分类号: G06F9/44 G06F9/45

    摘要: Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

    摘要翻译: 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息,包括原始分支指令的原始目标地址。 此外,机制重写原始分支指令,使得重写的分支指令的目标引用分支存根。 此外,机制输出编译代码,包括重写的分支指令和分支存根,以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令,而无需指令高速缓存运行时系统的干预 。

    Binary Rewriting in Software Instruction Cache
    27.
    发明申请
    Binary Rewriting in Software Instruction Cache 有权
    软件指令缓存中的二进制重写

    公开(公告)号:US20120198169A1

    公开(公告)日:2012-08-02

    申请号:US13442919

    申请日:2012-04-10

    IPC分类号: G06F9/38 G06F12/08

    CPC分类号: G06F9/3806 G06F12/0875

    摘要: Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

    摘要翻译: 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外,响应于确定目标指令存在于指令高速缓存中,机制直接将代码部分的执行分支到指令高速缓存中的目标指令,而不需要来自指令高速缓存运行时系统的干预。 此外,响应于确定目标指令不能被确定为存在于指令高速缓存中,机制将代码部分的执行重定向到指令高速缓存运行时系统。

    Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
    28.
    发明申请
    Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction 审中-公开
    动态重写缓存线驱逐响应中的分支指令

    公开(公告)号:US20110320786A1

    公开(公告)日:2011-12-29

    申请号:US12823226

    申请日:2010-06-25

    IPC分类号: G06F9/38 G06F9/45 G06F12/08

    摘要: Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

    摘要翻译: 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分,直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令,其直接或间接地对目标当前高速缓存行中的代码部分。 此外,重写一个或多个重写的分支指令,以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

    System and method for photorealistic imaging using ambient occlusion
    30.
    发明授权
    System and method for photorealistic imaging using ambient occlusion 有权
    使用环境遮挡的真实感成像系统和方法

    公开(公告)号:US09483864B2

    公开(公告)日:2016-11-01

    申请号:US12329470

    申请日:2008-12-05

    IPC分类号: G06T15/50 G06T15/06

    CPC分类号: G06T15/06

    摘要: Scene model data, including a scene geometry model and a plurality of pixel data describing objects arranged in a scene, is received. A primary pixel color and a primary ray are generated based on a selected first pixel data. If the primary ray intersects an object in the scene, an intersection point is determined. A surface normal is determined based on the object intersected and the intersection point. The primary pixel color is modified based on a primary hit color, determined based on the intersection point. A plurality of ambient occlusion (AO) rays each having a direction, D, are generated based on the intersection point, P and the surface normal. Each AO ray direction is reversed and the AO ray origin is set to a point outside the scene. An AO ray that does not intersect an object before reaching the intersection point is included in ambient occlusion calculations. The primary pixel color is shaded based on the ambient occlusion and the primary hit color and an image is generated based on the primary pixel color for the pixel data.

    摘要翻译: 接收场景模型数据,包括场景几何模型和描述在场景中布置的对象的多个像素数据。 基于所选择的第一像素数据生成主要像素颜色和主要光线。 如果主光线与场景中的对象相交,则确定交点。 基于相交对象和交点确定表面法线。 基于基于交点确定的主要命中颜色修改主像素颜色。 基于交点P和表面法线,生成各自具有方向D的多个环境遮挡(AO)射线。 每个AO射线方向相反,并将AO射线原点设置为场景外的点。 在到达交点之前不与物体相交的AO射线被包括在环境遮挡计算中。 主像素颜色基于环境遮挡和主要命中颜色而阴影,并且基于像素数据的主像素颜色生成图像。