公开(公告)号：US20110321021A1

公开(公告)日：2011-12-29

申请号：US12823244

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

摘要翻译： 提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。 这些机制产生一部分代码的调用图。 调用图中的节点和边被加权以生成加权调用图。 然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码 调用图被组合到基于分区的各个高速缓存行。 然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

公开(公告)号：US20110321002A1

公开(公告)日：2011-12-29

申请号：US12823204

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/4436 ,  G06F8/433 ,  G06F8/4442

摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

摘要翻译： 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。 此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。 此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预 。

公开(公告)号：US20120204016A1

公开(公告)日：2012-08-09

申请号：US13443188

申请日：2012-04-10

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/318

CPC分类号： G06F8/4436 ,  G06F8/433 ,  G06F8/4442

摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

摘要翻译： 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。 此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。 此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预 。

公开(公告)号：US20120198170A1

公开(公告)日：2012-08-02

申请号：US13444890

申请日：2012-04-12

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

公开(公告)号：US20110320785A1

公开(公告)日：2011-12-29

申请号：US12823194

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/318

CPC分类号： G06F9/3806 ,  G06F12/0875

摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，机制将代码部分的执行重定向到指令高速缓存运行时系统。

公开(公告)号：US20120198429A1

公开(公告)日：2012-08-02

申请号：US13444907

申请日：2012-04-12

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

摘要翻译： 提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。 这些机制产生一部分代码的调用图。 调用图中的节点和边被加权以生成加权调用图。 然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码 调用图被组合到基于分区的各个高速缓存行。 然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

公开(公告)号：US20120198169A1

公开(公告)日：2012-08-02

申请号：US13442919

申请日：2012-04-10

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F12/0875

摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，机制将代码部分的执行重定向到指令高速缓存运行时系统。

公开(公告)号：US20110320786A1

公开(公告)日：2011-12-29

申请号：US12823226

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/38 ,  G06F9/45 ,  G06F12/08

CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

公开(公告)号：US08782381B2

公开(公告)日：2014-07-15

申请号：US13444890

申请日：2012-04-12

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/44

CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

公开(公告)号：US08627051B2

公开(公告)日：2014-01-07

申请号：US13442919

申请日：2012-04-10

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/44

CPC分类号： G06F9/3806 ,  G06F12/0875

摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。