公开(公告)号：US11429535B1

公开(公告)日：2022-08-30

申请号：US17372356

申请日：2021-07-09

Applicant: Apple Inc.

Inventor： Brian R. Mestan ,  Peter G. Soderquist

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/0817 ,  G06F12/128 ,  G06F12/0811

Abstract: Techniques are disclosed relating to controlling cache replacement. In some embodiments, search control circuitry is configured to perform multiple searches of a data structure (e.g., page table walks) where searches traverse multiple links between elements of the data structure. In some embodiments, a traversal cache caches traversal information that is usable by searches to skip one or more links traversed by one or more prior searches. In some embodiments, tracking control circuitry stores tracking information in a first entry, where the tracking information indicates a location in the traversal cache at which prior traversal information for a first search is stored. In some embodiments, replacement control circuitry selects, based on the tracking information in the first entry of the tracking control circuitry, an entry in the traversal cache for new traversal information generated by the first search (which may include selecting the first entry to override a default replacement policy).

公开(公告)号：US20220091846A1

公开(公告)日：2022-03-24

申请号：US17473076

申请日：2021-09-13

Applicant: Apple Inc.

Inventor： Brian R. Mestan ,  Gideon N. Levinsky ,  Michael L. Karm

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F9/52

Abstract: In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.

公开(公告)号：US10909035B2

公开(公告)日：2021-02-02

申请号：US16374667

申请日：2019-04-03

Applicant: Apple Inc.

Inventor： Brian R. Mestan

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0837 ,  G06F9/30

Abstract: A system and method for efficiently supporting a cache memory hierarchy potentially using a zero size cache in a level of the hierarchy. In various embodiments, logic in a lower-level cache controller or elsewhere receives a miss request from an upper-level cache controller. When the requested data is non-cacheable, the logic sends a snoop request with an address of the memory access operation to the upper-level cache controller to determine whether the requested data is in the upper-level data cache. When the snoop response indicates a miss or the requested data is cacheable, the logic retrieves the requested data from memory. When the snoop response indicates a hit, the logic retrieves the requested data from the upper-level cache. The logic completes servicing the memory access operation while preventing cache storage of the received requested data in a cache at a same level of the cache memory hierarchy as the logic.

公开(公告)号：US20200264888A1

公开(公告)日：2020-08-20

申请号：US16277764

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Deepak Limaye ,  Brian R. Mestan ,  Gideon N. Levinsky

IPC: G06F9/38 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0815

Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.