公开(公告)号：US11347514B2

公开(公告)日：2022-05-31

申请号：US16277764

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Deepak Limaye ,  Brian R. Mestan ,  Gideon N. Levinsky

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0864

Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

公开(公告)号：US11099990B2

公开(公告)日：2021-08-24

申请号：US16545521

申请日：2019-08-20

Applicant: Apple Inc.

Inventor： Gideon N. Levinsky ,  Brian R. Mestan ,  Deepak Limaye ,  Mridul Agarwal

IPC: G06F12/0811

Abstract: A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.

公开(公告)号：US20210056024A1

公开(公告)日：2021-02-25

申请号：US16545521

申请日：2019-08-20

Applicant: Apple Inc.

Inventor： Gideon N. Levinsky ,  Brian R. Mestan ,  Deepak Limaye ,  Mridul Agarwal

IPC: G06F12/0811

Abstract: A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.

公开(公告)号：US11893413B2

公开(公告)日：2024-02-06

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5016 ,  G06F9/5022

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US20220083369A1

公开(公告)日：2022-03-17

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/54

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US20200264888A1

公开(公告)日：2020-08-20

申请号：US16277764

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Deepak Limaye ,  Brian R. Mestan ,  Gideon N. Levinsky

IPC: G06F9/38 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0815

Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

公开(公告)号：US20190220417A1

公开(公告)日：2019-07-18

申请号：US15874624

申请日：2018-01-18

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Deepak Limaye ,  James N. Hardage

IPC: G06F12/12 ,  G06F9/46 ,  G06F8/41 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/12 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/461

Abstract: In an embodiment, a processor may include a register file including one or more sets of registers for one or more data types specified by the ISA implemented by the processor. The processor may have a processor mode in which the context is reduced, as compared to the full context. For example, for at least one of the data types, the registers included in the reduced context exclude one or more of the registers defined in the ISA for that data type. In an embodiment, one half or more of the registers for the data type may be excluded. When the processor is operating in a reduced context mode, the processor may detect instructions that use excluded registers, and may signal an exception for such instructions to prevent use of the excluded registers.