公开(公告)号：US20190172485A1

公开(公告)日：2019-06-06

申请号：US16272183

申请日：2019-02-11

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  H01L21/768 ,  G11B5/31 ,  G11C11/15

Abstract: Embodiments herein provide methods of forming a magnetic tunnel junction structure. The method includes forming a film stack that includes: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru; and forming a magnetic tunnel junction structure.

公开(公告)号：US20150255507A1

公开(公告)日：2015-09-10

申请号：US14201439

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Mahendra PAKALA ,  Mihaela BALSEANU ,  Jonathan GERMAIN ,  Jaesoo AHN ,  Lin XUE

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

Abstract translation: 公开了一种用于制造MRAM位的方法，其包括在处理期间沉积保护隧道势垒层的间隔层。 沉积的间隔层防止在后续处理中形成的副产物再沉积在隧道势垒层上。 这种再沉积可能导致产品失效并降低了制造成品率。 该方法还包括防腐损坏处理条件，以防损坏MRAM位的层。 非腐蚀性处理条件可以包括不使用卤素等离子体的蚀刻。 本文公开的实施例使用简化处理的蚀刻 - 沉积蚀刻序列。