公开(公告)号：US20210064528A1

公开(公告)日：2021-03-04

申请号：US16550607

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ ,  Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/1027

Abstract: A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.

公开(公告)号：US20210026632A1

公开(公告)日：2021-01-28

申请号：US16521663

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Miles Robert DOOLEY ,  Balaji VIJAYAN ,  Huzefa Moiz SANJELIWALA ,  . ABHISHEK RAJA ,  Sharmila SHRIDHAR

IPC: G06F9/30

Abstract: An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.