公开(公告)号：US20190340124A1

公开(公告)日：2019-11-07

申请号：US16305165

申请日：2017-04-27

Applicant: ARM LIMITED

Inventor： Adnan KHAN ,  Alex James WAUGH ,  Jose GONZALEZ-GONZALEZ

IPC: G06F12/084 ,  G06F12/0817 ,  G06F12/0831

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

公开(公告)号：US20170109289A1

公开(公告)日：2017-04-20

申请号：US15271611

申请日：2016-09-21

Applicant: ARM Limited

Inventor： Jose GONZALEZ GONZALEZ ,  Alex James WAUGH ,  Adnan KHAN

IPC: G06F12/0895 ,  G06F12/1045

CPC classification number: G06F12/0895 ,  G06F12/0833 ,  G06F12/1063 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/152

Abstract: An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists. Further, snoop request processing circuitry is provided that is responsive to a snoop request specifying a physical address, to determine a plurality of possible virtual address portions for the physical address, and to perform a snoop processing operation in order to determine whether the hit condition is detected for a cache entry when accessing the cache storage using the plurality of possible virtual address portions. On detection of the hit condition a coherency action is performed in respect of the cache entry causing the hit condition. This allows effective detection and removal of aliasing conditions that can arise when different virtual addresses associated with the same physical address cause cache entries in different sets of the cache to be accessed.

公开(公告)号：US20170060175A1

公开(公告)日：2017-03-02

申请号：US15227051

申请日：2016-08-03

Applicant: ARM LIMITED

Inventor： Alex James WAUGH

IPC: G06F1/14 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/26

Abstract: An apparatus includes control circuitry configured to receive a first N-bit count value in a first domain, and to determine an M-bit increment indicating value based on the first N-bit count value and a reference value, where M

Abstract translation: 一种装置包括控制电路，其被配置为在第一域中接收第一N位计数值，并且基于第一N位计数值和参考值确定M位增量指示值，其中M