公开(公告)号：US20180365151A1

公开(公告)日：2018-12-20

申请号：US15833497

申请日：2017-12-06

申请人： International Business Machines Corporation

发明人： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC分类号： G06F12/0817 ,  G06F12/0842 ,  G06F12/0831

CPC分类号： G06F12/0828 ,  G06F12/0822 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1024

摘要： A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：US20180276133A1

公开(公告)日：2018-09-27

申请号：US15990558

申请日：2018-05-25

申请人： International Business Machines Corporation

发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Benhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

IPC分类号： G06F12/0879 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0802 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/0831 ,  G06F12/127

CPC分类号： G06F12/0879 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/127 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/303 ,  G06F2212/604 ,  G06F2212/62 ,  G06F2212/657

摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

公开(公告)号：US10061700B1

公开(公告)日：2018-08-28

申请号：US15230230

申请日：2016-08-05

申请人： Amazon Technologies, Inc.

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08 ,  G06F12/0817 ,  G06F12/0855

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US20180225209A1

公开(公告)日：2018-08-09

申请号：US15427320

申请日：2017-02-08

申请人： ARM Limited

发明人： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Mark David WERKHEISER

IPC分类号： G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

CPC分类号： G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/302 ,  G06F2212/6042

摘要： A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

公开(公告)号：US20180203811A1

公开(公告)日：2018-07-19

申请号：US15918895

申请日：2018-03-12

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Ashish Gupta

IPC分类号： G06F13/22 ,  G06F1/32 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.

公开(公告)号：US09990293B2

公开(公告)日：2018-06-05

申请号：US14457128

申请日：2014-08-12

申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC

发明人： Yan Solihin

IPC分类号： G06F12/08 ,  G06F12/12 ,  G11C7/10 ,  G06F12/0831 ,  G06F12/0811 ,  G11C11/401 ,  G11C11/406 ,  G06F12/123

CPC分类号： G06F12/0833 ,  G06F12/0811 ,  G06F12/123 ,  G06F2212/1024 ,  G11C7/1072 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40622 ,  Y02D10/13

摘要： Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.

公开(公告)号：US20180139281A1

公开(公告)日：2018-05-17

申请号：US15811801

申请日：2017-11-14

申请人： NetApp Inc.

发明人： Dhananjoy Das

IPC分类号： H04L29/08 ,  G06F13/28 ,  G06F15/173 ,  G06F3/06

CPC分类号： H04L67/1097 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0833 ,  G06F13/28 ,  G06F15/17331 ,  G06F2212/62 ,  H04L67/1095 ,  H04L67/2842

摘要： A method for enforcing data integrity in an RDMA data storage system includes flushing data write requests to a data storage device before sending an acknowledgment that the data write requests have been executed. An RDMA data storage system includes a node configured to flush data write requests to a data storage device before sending an acknowledgment that a data write request has been executed.

公开(公告)号：US20180101476A1

公开(公告)日：2018-04-12

申请号：US15288792

申请日：2016-10-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： BERNARD C. DRERUP ,  RAM RAGHAVAN ,  SAHIL SABHARWAL ,  JEFFREY A. STUECHELI

IPC分类号： G06F12/0864 ,  G06F12/128

CPC分类号： G06F12/0864 ,  G06F12/0833 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  G06F2212/69 ,  G06F2212/70

摘要： A set-associative cache memory includes a bank of counters including a respective one of a plurality of counters for each cache line stored in a plurality of congruence classes of the cache memory. Prior to receiving a memory access request that maps to a particular congruence class of the cache memory, the cache memory pre-selects a first victim cache line stored in a particular entry of a particular congruence class for eviction based on at least a counter value of the victim cache line. In response to receiving a memory access request that maps to the particular congruence class and that misses, the cache memory evicts the pre-selected first victim cache line from the particular entry, installs a new cache line in the particular entry, and pre-selects a second victim cache line from the particular congruence class based on at least a counter value of the second victim cache line.

公开(公告)号：US20180095927A1

公开(公告)日：2018-04-05

申请号：US15821401

申请日：2017-11-22

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  Darren S. Jue ,  Rahul C. Shah ,  Arvind A. Kumar

IPC分类号： G06F13/42 ,  H04L12/933 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F13/40 ,  H04L12/46 ,  H04L12/741

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

公开(公告)号：US09921913B2

公开(公告)日：2018-03-20

申请号：US15153491

申请日：2016-05-12

申请人： Dell Products L.P.

发明人： Deepu Syam Sreedhar M. ,  Sandeep Agarwal ,  Krishna Kumar P. K. ,  Sujoy Sen ,  Somashekar Ajjampur Manjunatha

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0868

CPC分类号： G06F11/1092 ,  G06F11/1084 ,  G06F12/0833 ,  G06F12/0868 ,  G06F12/128 ,  G06F2211/1009 ,  G06F2212/224 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

摘要： A storage management method includes receiving a degrade signal indicating a degraded state of a virtual disk associated with a host system. Rebuild-flush operations may be performed. The operations may include writing, to the virtual disk and also to a hot spare drive (HSP) associated with the virtual disk, valid-modified data, stored in a host storage cache, associated with the virtual disk. In contrast, valid-unmodified storage cache data associated with the virtual disk, may be written to the HSP only. After the rebuild-flush completes, the virtual disk may be rebuilt. During rebuild, however, any cached-LBA may be skipped where traditional RAID rebuild operations are performed for un-cached LBAs only.