公开(公告)号：US10268581B2

公开(公告)日：2019-04-23

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael Filippo ,  Klas Magnus Bruce ,  Vasu Kudaravalli ,  Adam George ,  Muhammad Umar Farooq ,  Joseph Michael Pusdesris

IPC: G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US09880961B2

公开(公告)日：2018-01-30

申请号：US14092417

申请日：2013-11-27

Applicant: ARM LIMITED

Inventor： Brett Stanley Feero ,  Klas Magnus Bruce

IPC: G06F1/04 ,  G06F1/12 ,  G06F13/40

CPC classification number: G06F13/4059 ,  G06F2213/0038

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.