公开(公告)号：US11269773B2

公开(公告)日：2022-03-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Andrew John Turner

IPC: G06F9/52 ,  G06F9/30 ,  G06F15/78 ,  G06F13/42 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0815

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US20200097410A1

公开(公告)日：2020-03-26

申请号：US16139517

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Adrian Montero ,  Klas Magnus Bruce ,  Chris Abernathy

IPC: G06F12/0862 ,  G06F12/0871 ,  G06F11/34

Abstract: The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.

公开(公告)号：US12174753B2

公开(公告)日：2024-12-24

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Klas Magnus Bruce ,  Jamshed Jalal ,  Dimitrios Kaseridis ,  Gurunath Ramagiri ,  Ho-Seop Kim ,  Andrew John Turner ,  Rania Hussein Hassan Mameesh

IPC: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

公开(公告)号：US11593025B2

公开(公告)日：2023-02-28

申请号：US16743409

申请日：2020-01-15

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Klas Magnus Bruce ,  Ritukar Khanna

IPC: G06F3/06

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

公开(公告)号：US11159636B2

公开(公告)日：2021-10-26

申请号：US15427384

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

IPC: H04L29/08 ,  G06F12/0831

Abstract: A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.

公开(公告)号：US10402349B2

公开(公告)日：2019-09-03

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US10983916B2

公开(公告)日：2021-04-20

申请号：US15446235

申请日：2017-03-01

Applicant: ARM Limited

Inventor： Huzefa Moiz Sanjeliwala ,  Klas Magnus Bruce ,  Leigang Kou ,  Michael Filippo ,  Miles Robert Dooley ,  Matthew Andrew Rafacz

IPC: G06F12/00 ,  G06F12/0897 ,  G06F12/0862

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.

公开(公告)号：US10810126B2

公开(公告)日：2020-10-20

申请号：US16139517

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Adrian Montero ,  Klas Magnus Bruce ,  Chris Abernathy

IPC: G06F12/08 ,  G06F12/0862 ,  G06F11/34 ,  G06F12/0871

Abstract: The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.

公开(公告)号：US10776043B2

公开(公告)日：2020-09-15

申请号：US16118610

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Adrian Montero ,  Miles Robert Dooley ,  Joseph Michael Pusdesris ,  Klas Magnus Bruce ,  Chris Abernathy

IPC: G06F3/06 ,  G11B19/04 ,  G06F9/50 ,  G06F12/0862 ,  G06F12/0815

Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.