DISPLAY SUBSTRATE AND DISPLAY DEVICE

    公开(公告)号:US20240397650A1

    公开(公告)日:2024-11-28

    申请号:US18696957

    申请日:2023-07-04

    Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate including a display area and a first frame area located on one side of the display area; and a first power bus at least located in the first frame area. The first power bus includes a first sub-bus, a second sub-bus and at least two connecting wires. The first sub-bus is located between the second sub-bus and the display area, and the first sub-bus is electrically connected to the second sub-bus by means of the at least two connecting wires.

    DISPLAY SUBSTRATE
    22.
    发明申请

    公开(公告)号:US20240381716A1

    公开(公告)日:2024-11-14

    申请号:US18249397

    申请日:2022-05-20

    Abstract: The disclosure provides a display substrate, which has a display region and a peripheral region, and includes a base substrate, a plurality of sub-pixels, a first power signal line and a second power signal line at least partially located in the display region, a first power signal bus and a second power signal bus located in the peripheral region; the sub-pixels are located in the display region; the first power signal line and the second power signal line are electrically connected to the first power signal bus and the second power signal bus, respectively; the second power signal bus includes a first part disposed on a side of the first power signal bus close to the display region, and a second part disposed on a side of the first power signal bus away from the display region, so as to at least partially surround the first power signal bus.

    ARRAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE

    公开(公告)号:US20210296406A1

    公开(公告)日:2021-09-23

    申请号:US17264283

    申请日:2020-05-12

    Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

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