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1.发明申请公开(公告)号：US20210225886A1
公开(公告)日：2021-07-22
申请号：US16936447
申请日：2020-07-23
发明人： Qinghe WANG , Tongshang SU , Yongchao HUANG , Yingbin HU , Yang ZHANG , Haitao WANG , Ning LIU , Guangyao LI , Zheng WANG , Yu JI , Jinliang HU , Wei SONG , Jun CHENG , Liangchen YAN
IPC分类号： H01L27/12 , H01L29/786 , H01L29/24 , H01L29/66
摘要： A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer.
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公开(公告)号：US20240215342A1
公开(公告)日：2024-06-27
申请号：US17915522
申请日：2021-05-28
发明人： Yongchao HUANG , Jingang FANG , Jun CHENG , Xinxin WANG , Jun LIU , Qinghe WANG , Leilei CHENG , Bin ZHOU , Ce ZHAO , Liangchen YAN
IPC分类号： H10K59/126 , H10K59/12 , H10K59/122
CPC分类号： H10K59/126 , H10K59/1201 , H10K59/122
摘要： A display panel includes a substrate, a driving layer and a light-emitting control layer. The driving layer is provided with a plurality of driving transistors arranged into a plurality of transistor rows in a column direction. The light-emitting control layer includes a plurality of light-emitting devices arranged into a plurality of device rows in the column direction, the device rows is spaced apart by the transistor row in the column direction, and the transistor rows is spaced apart by the device row in the column direction. The pixel-defining layer is provided with a plurality of blocking grooves recessed toward the substrate, the plurality of blocking grooves are arranged in the column direction, at least one of the plurality of blocking grooves is arranged between the transistor row and the device row adjacent in the column direction, and a light-shielding layer is arranged in the blocking groove.
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公开(公告)号：US20230200128A1
公开(公告)日：2023-06-22
申请号：US17615835
申请日：2021-02-26
发明人： Tongshang SU , Bin ZHOU , Jun CHENG , Qinghe WANG , Yongchao HUANG , Dacheng ZHANG , Liangchen YAN
IPC分类号： H10K59/121 , H10K59/35 , H10K59/12 , H10K71/00 , H10K59/122
CPC分类号： H10K59/1213 , H10K59/353 , H10K59/1201 , H10K71/00 , H10K59/122
摘要： The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a drive circuit layer disposed on a base substrate and a light emitting structure layer disposed on a side of the drive circuit layer away from the base substrate. The light emitting structure layer includes an anode, an organic light emitting layer, a cathode, and an auxiliary electrode. The organic light emitting layer is respectively connected to the anode and the cathode, and the cathode is connected to the auxiliary electrode; in a plane parallel to the display substrate, an edge of the auxiliary electrode is provided with a structure depressed towards a center of the auxiliary electrode.
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4.发明申请公开(公告)号：US20220352382A1
公开(公告)日：2022-11-03
申请号：US17765238
申请日：2021-05-20
发明人： Qinghe WANG , Tongshang SU , Jun WANG , Yongchao HUANG , Haitao WANG , Ning LIU , Jun CHENG , Yingbin HU
IPC分类号： H01L29/786 , G11C19/28 , H01L29/66
摘要： A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.
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公开(公告)号：US20210066352A1
公开(公告)日：2021-03-04
申请号：US16919903
申请日：2020-07-02
发明人： Leilei CHENG , Bin ZHOU , Jun LIU , Luke DING , Qinghe WANG , Yongchao HUANG
IPC分类号： H01L27/12 , G02F1/1333 , G02F1/1362
摘要： An array substrate includes an insulation layer and one or more stepped holes each penetrating through the insulation layer in a direction perpendicular to the insulation layer. Each stepped hole includes a first hole and a second hole under the first hole, a radius of the first hole at a bottom is a first radius, a radius of the second hole at a top is a second radius which is substantially smaller than the first radius, and a difference between the first radius and the second radius is 0.2 μm to 0.6 μm.
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公开(公告)号：US20240292688A1
公开(公告)日：2024-08-29
申请号：US18026752
申请日：2022-06-21
发明人： Jun WANG , Jun CHENG , Haitao WANG , Tongshang SU , Yongchao HUANG , Jingang FANG , Liu ZHANG , Shengli LIU , Hongzheng WANG
IPC分类号： H10K59/131 , H10K59/80 , H10K102/00 , H10K102/10
CPC分类号： H10K59/131 , H10K59/80517 , H10K59/80518 , H10K59/873 , H10K2102/103 , H10K2102/3026
摘要： Provided is a display substrate, including: a base, a first signal line, a second signal line, and a first electrode. The first signal line, the second signal line and the first electrode are located on the base and sequentially arranged away from the base, and are insulated from each other; orthographic projections of the first signal line and the second signal line on the base at least partially overlap, an orthographic projection of the first electrode partially overlaps with an overlapping region in which the orthographic projections of the first signal line and the second signal line on the base overlap; an opening is provided in at least a partial region of the first electrode, with the orthographic projection thereof on the base overlaps with the overlapping region in which the orthographic projections of the first signal line and the second signal line on the base overlap with each other.
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公开(公告)号：US20240213278A1
公开(公告)日：2024-06-27
申请号：US17913808
申请日：2021-10-26
发明人： Haitao WANG , Ming WANG , Jun CHENG , Bin ZHOU , Jun WANG , Yongchao HUANG , Tongshang SU , Qinghe WANG
IPC分类号： H01L27/12
CPC分类号： H01L27/1288 , H01L27/124
摘要： The present disclosure provides a method for manufacturing a display panel, a display panel and a to-be-cut display panel, and relates to the field of display technologies. The method includes: forming a first electrostatic protective circuit and a source and drain conductive pattern on a base substrate; removing the source and drain conductive pattern within the target cutting region; forming a to-be-cut display panel by forming a superstructure on the base substrate; and cutting the to-be-cut display panel in the target cutting region. When manufacturing the internal structure of the display panel, only the source and drain conductive pattern in the target cutting region is removed, while the electrostatic protective circuit in the target cutting region is retained. In this way, the electrostatic protective circuit can always play the function of electrostatic protective during the formation of the internal structure of the display panel, such that the internal structure of the display panel is avoided from being damaged by electrostatic, the manufacturing yield of the display panel improved, the problem of low manufacturing yield of the display panel in the related technology is solved, and the effect of improving the manufacturing yield of the display panel is achieved.
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公开(公告)号：US20230380215A1
公开(公告)日：2023-11-23
申请号：US17432462
申请日：2021-02-24
发明人： Leilei CHENG , Yongchao HUANG , Qinghe WANG , Yang ZHANG , Bin ZHOU
CPC分类号： H10K59/1201 , H10K71/20 , H10K77/10 , H10K59/82 , H10K59/87 , H10K59/32 , H10K59/1213 , G02F1/1306
摘要： The disclosure relates to the technical field of display, in particular to a displaying substrate, a manufacturing method thereof and a display panel. The displaying substrate comprises a passivation layer (28) and a flat layer (29) covering the passivation layer (28), wherein the flat layer (29) comprises a first flat via hole and a plurality of second flat via holes, the passivation layer (28) comprises a first passivation via hole, and the first flat via hole and the first passivation via hole form a first sleeve hole (31); and the hole depth of the first flat via hole is smaller than that of each second flat via hole, and the hole depth of the first passivation via hole is greater than or equal to the difference between the maximum hole depth of all the second flat via holes and the hole depth of the first flat via hole.
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公开(公告)号：US20220255038A1
公开(公告)日：2022-08-11
申请号：US17481327
申请日：2021-09-22
发明人： Qinghe WANG , Jun CHENG , Tongshang SU , Ning LIU , Haitao WANG , Yongchao HUANG , Jingang FANG , Liusong NI , Liangchen YAN
摘要： Provided are a display substrate and a display apparatus. The display substrate includes a base substrate, and an auxiliary cathode structure located on a side of the base substrate, the auxiliary cathode structure including a first conductive layer, an intermediate support layer, and a second conductive layer. In an implementation, a side of the intermediate support layer close to the first conductive layer includes any one or more of first protrusions and first grooves, and a side of the first conductive layer close to the intermediate support layer includes any one or more of second grooves engaged with the first protrusions and second protrusions engaged with the first grooves which are correspondingly disposed.
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公开(公告)号：US20210335245A1
公开(公告)日：2021-10-28
申请号：US17259702
申请日：2020-06-24
IPC分类号： G09G3/3233 , G09G3/3275 , G09G3/32
摘要： A method for controlling a charging time of a display panel includes: during t0+kΔt in a (k+1)-th blanking time, writing a data voltage to a gate of a driving transistor, and detecting a voltage Vk_(j,i) of a second electrode of the driving transistor; during a t0+(k+r)Δt in a (k+1+r)-th blanking time, writing the data voltage to the gate of the driving transistor, and detecting a voltage Vk+i_(j,i) of the second electrode of the driving transistor; determining whether ΔVj,i=Vk+1_ji−Vk_ji is less than or equal to a target voltage difference VT; if ΔVj,i≤VT, taking the T=t0+kΔt as an expected charging time of a sub-pixel; if ΔVj,i>VT, cyclically performing the charging step described above to obtain ΔVj,i=Vk+p+1_(j,i)−Vk+p_(j,i), and comparing ΔVj,i with the target voltage difference VT, until ΔVj,i≤VT, taking t0+(k+p+r−1)Δt as the expected charging time of the sub-pixel. p is taken from 1, and increases by 1 for each cycle.
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