Method for forming a shallow junction in a semiconductor device using antimony dimer
    21.
    发明授权
    Method for forming a shallow junction in a semiconductor device using antimony dimer 有权
    使用锑二聚体在半导体器件中形成浅结的方法

    公开(公告)号:US06191012B1

    公开(公告)日:2001-02-20

    申请号:US09205522

    申请日:1998-12-03

    CPC classification number: H01L29/6659 H01L21/26513 H01L21/2658

    Abstract: A method for forming a shallow junction in a semiconductor device includes the steps of ion implanting a molecular antimony dimer (Sb2+) into a semiconductor substrate. The antimony dimer implantation process creates a shallow doped junction having a high dopant concentration and a shallow junction depth. The antimony dimer ion is extracted from an antimony source material at an extremely low extraction voltage. The use of a low extraction voltage enables the antimony dimer ion to be analyzed by an analyzer magnetic within the ion implantation device. The process of the invention can be used to form a variety of shallow dope structures in semiconductor devices, such as source/drain extension regions, implanted resistors, and the like.

    Abstract translation: 在半导体器件中形成浅结的方法包括将分子锑二聚体(Sb 2+)离子注入到半导体衬底中的步骤。 锑二聚体注入工艺产生具有高掺杂浓度和浅结深度的浅掺杂结。 锑二聚体离子以极低的提取电压从锑源材料中提取。 使用低提取电压使得锑二聚体离子能够通过离子注入装置内的分析仪磁体进行分析。 本发明的方法可用于在半导体器件中形成多种浅掺杂结构,例如源极/漏极延伸区域,注入的电阻器等。

    End-of-range damage suppression for ultra-shallow junction formation
    22.
    发明授权
    End-of-range damage suppression for ultra-shallow junction formation 失效
    超浅结点形成的终点范围损伤抑制

    公开(公告)号:US6074937A

    公开(公告)日:2000-06-13

    申请号:US58897

    申请日:1998-04-13

    CPC classification number: H01L29/6659 H01L21/26506 H01L21/2652

    Abstract: Lightly doped regions are implanted into an amorphous region in the semiconductor substrate to significantly reduce transient enhanced diffusion upon subsequent activation annealing. A sub-surface non-amorphous region is also formed before activation annealing to substantially eliminate end-of-range defects on crystallization of amorphous region containing the lightly doped implants.

    Abstract translation: 将轻掺杂区域注入到半导体衬底中的非晶区域中,以在随后的激活退火时显着减少瞬时增强的扩散。 在激活退火之前还形成亚表面非非晶区域,以基本上消除含有轻掺杂植入物的非晶区域的结晶范围内的范围内缺陷。

    Virtual hard mask for etching
    23.
    发明授权
    Virtual hard mask for etching 失效
    用于蚀刻的虚拟硬掩模

    公开(公告)号:US5876903A

    公开(公告)日:1999-03-02

    申请号:US774581

    申请日:1996-12-31

    CPC classification number: G03F7/40 H01L21/0274 G03F7/2024 G03F7/203

    Abstract: A method of hardening photoresist (24) by bombardment with ionized particles (42), such as argon. Ionic bombardment causes formation of a hardened skin (22) on the exposed top (30) and side walls (32) of the photoresist (24). The hardened skin erodes at a reduced rate during etching and is less likely to react with products created during etching, thereby allowing etching of more accurate line widths and gaps.

    Abstract translation: 通过用诸如氩的电离粒子(42)轰击来硬化光致抗蚀剂(24)的方法。 离子轰击导致在光致抗蚀剂(24)的暴露的顶部(30)和侧壁​​(32)上形成硬化的皮肤(22)。 硬化的皮肤在蚀刻期间以降低的速率腐蚀,并且不太可能与蚀刻期间产生的产物反应,从而允许蚀刻更精确的线宽和间隙。

Patent Agency Ranking