摘要:
According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.
摘要:
In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possible latch values that each corresponds to a different configuration of the functional portion of the digital system. With one or more statements in the one or more files, a multi-level Dial tree is defined that includes a selective control Dial (SCDial) entity at an upper level that is associated with at least one design entity. The SCDial entity has a Dial input, a plurality of Dial outputs coupled to inputs of the plurality of lower level Dials, and a mapping table indicating a mapping between each of a plurality of possible input values of the Dial input and a respective one of a plurality of sets of output values for the plurality of Dial outputs. At least one set of output values in the mapping table specifies output values for fewer than all of the plurality of Dial outputs. Each specified output value reflects a setting of at least one lower level Dial, and settings of the lower level Dials reflect which of the plurality of different possible configuration values is loaded in the plurality of configuration latches.
摘要:
Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.
摘要:
According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.
摘要:
According to one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and a threshold greater than 1 is established for the count event counter. The design is then simulated utilizing the HDL simulation model, and occurrences of the count event are accumulated in the count event counter to obtain a count event value. Thereafter, an indication of whether the count event value of the count event exceeds the threshold is recorded within a data storage subsystem.
摘要:
In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which value is loaded in the associated latch. A controlling value set, indicating at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted, is also defined in one or more files. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.
摘要:
A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.
摘要:
In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instrumentation entities monitor logical operation of one or more of the plurality of design entities during simulation for occurrence of events of interest. In response to the indication, the compiler determines by reference to a bill-of-materials of a previously compiled file whether or not the previously compiled file was compiled with instrumentation entities compatible with the desired set of instrumentation entities. In response to determining that the previously compiled file was compiled with compatible instrumentation entities, the compiler compiles the simulation model of the digital design utilizing the previously compiled file in accordance with the indication.
摘要:
A method and system for tracking instances of a testcase execution event within a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a design entity list is generated within the HDL model, wherein the design entity list identifies all design entities instantiated within the HDL model. One or more instrumentation code modules are dynamically loaded into the simulation control program, wherein the instrumentation code modules generate and process testcase execution events associated with at least one of the identified design entities.
摘要:
A method and system for minimizing redundancy in collected harvest event testcases from a batch simulation farm which includes a harvest testcase server that collects simulation data for a simulation model from at least one simulation client. In accordance with the method of the present invention, a testcase is executed on the simulation model within a simulation client. Responsive to the testcase triggering a harvest event, the harvest event is compared with a list of harvest events that have previously been triggered within the simulation model. In response to determining that the harvest event has not been previously triggered within the simulation model, the testcase is delivered to the harvest testcase server.