Abstract:
A data switching circuit is provided, which reduces power consumption of the source drivers when used together with a dot inversion driving method. The circuit comprises a control unit and a switching unit. Wherein, the control unit provides a switching signal. The switching unit has 2N input terminals and 2N output terminals and receives the switching signal. Assume that N is a positive integer and 1≦i≦N. When the switching signal is in a first state, the switching unit connects the (2i−1)th input terminal and the (2i−1)th output terminal, and connects the 2ith input terminal and the 2ith output terminal. When the switching signal is in a second state, the switching unit connects the 2ith input terminal and the (2i−1)th output terminal, and connects the (2i−1)th input terminal and the 2ith output terminal.
Abstract:
A display driving apparatus and a multi-line inversion driving method thereof are provided. The apparatus includes a gate driver, a source driver, a gate enabling unit and a line polarity signal unit. Every time after a plurality of scan lines is turned on, the source driver inverts the polarity of the sub pixel driving signal according to a line polarity signal output by the line polarity signal unit. Thereby, the polarity inversion operating frequency of the sub pixel driving signal is lowered to reduce the power consumption of the source driver.
Abstract:
A display system generates a plurality of sampling signals each having distinct phases based on external clock signals provided by a timing controller, latches data from external data signals provided by the timing controller based on the sampling signals, and sends the latched data to a decoder for determining a best sampling signal. Each driver of the display system generates driving voltages based on a respective best sampling signal determined by a respective decoder.
Abstract:
A source driver having a structure of adjusting voltage with speed is suitable for use in a panel displaying apparatus for driving a display array unit. The structure of adjusting voltage with speed has a logic speed monitoring unit, an internal logic voltage generator, a substrate voltage generator, a substrate leakage-current monitoring unit, and a power management control unit. In this manner, by monitoring the logic operation speed of an internal logic circuit in the source driver, in accordance with the change of the operation frequency, the power is dynamically adjusted, so as to optimize a condition between the power consumption and the operation speed. And, in the standby mode, the power consumption is further reduced by adjusting the substrate voltage. Also and, according to the substrate leakage current of the source driver, the substrate voltage can also be adjusted.
Abstract:
A wireless system broadcasts data in frames, each frame having F slots. Output from a matched filter is used to combine K slots to generate profile data, where K is less than F. N peak values respectively from n peak positions are selected from the profile data, where n is greater than one. A correlator is employed, together with the n peak positions and S slots subsequent the K slots, to generate n×S correlation values. Respective combination values for the n peak positions are generated by coherently combining the correlation values, and combining the coherent combination results with the non-coherent n peak values. The combination values are respectively used to generate SNR values for each of the n peak positions. The peak position having the best respective SNR value is then selected as a slot synchronization position.
Abstract:
A pixel matrix used in a liquid crystal display, including a plurality of pixel units. Each pixel unit includes a storage unit, a first switch and a second switch. The storage unit determines the displayed gray scale of the pixel unit according to a pixel voltage applied to the storage unit. The first switch is coupled between a first data line, a first scan line and the storage unit. The first switch connects or disconnects the first data line with the storage unit, according to the state of the signal on the first scan line. On the other hand, the second switch is coupled between a second data line, a second scan line and the storage unit. The second switch connects or disconnects the second data line with the storage unit, according to the state of the signal on the second scan line.
Abstract:
A source driver and an internal data transmission method are provided. The present invention employs specially designed switch units and creates specially designed data paths in a source driver, which matches with the driving method for dot invesion and the specially designed pixel array. When the dot inversion driving method is used on a pixel array of a specific design, each output buffer and digital-to-analog converter inside the source driver continuously output voltages of positive polarity and voltages of negative polarity, instead of switching between positive and negative polarities. Consequently, the swing voltages that the source driver outputs can be lowered, the power consumption can also be reduced accordingly, a smaller area is occupied, and the costs are reduced.
Abstract:
A soft-start high driving method and device to drive display panels are provided. The driving method includes the following steps. First, a display signal is provided for driving a display panel and displaying images. If no predetermined event happens, then, a high-driving mode is used for dynamically adjusting the driving capacity of the display signal. Finally, if a predetermined event happens, the soft-start high-driving mode is performed to dynamically adjust the driving capacity of the display signal.
Abstract:
A method and system for guard interval size and mode detection of a DVB signal. The detection system comprises guard interval detection systems (GIDS), each corresponding to a mode and performing parallel search for the guard interval size based on the OFDM symbol period of the mode. A correlation calculator of a GIDS calculates a correlation signal corresponding to each guard interval size. Characteristics such as maximum value, number of points above a threshold, and a maximum value position in a sample period for each correlation signal are determined and compared, and a valid guard interval size is selected according to the determined characteristics. A mode information combine block retrieves and analyses the detection result from the GIDS.
Abstract:
A driving circuit of a liquid crystal display is provided. The driving circuit comprises: a plurality of gate drivers for selectively driving a plurality of thin film transistors of the liquid crystal display; a plurality of source drivers for receiving an image signal, the plurality of source drivers cooperating with the plurality of gate drivers to display an image on the liquid crystal display, each of the plurality of source drivers further comprising an adjustable common voltage generating circuit, each the adjustable common voltage generating circuit compensating, a common voltage output from each the adjustable common voltage generating circuit to make each the common voltage output from each the adjustable common voltage generating circuit the same or to make each the common voltage output to an ITO layer of a panel of the liquid crystal display the same, based on a common voltage adjustable data and a clock signal; and a timing sequence controller for providing a control signal and a data flow to the plurality of gate drivers and the plurality of source drivers and providing the common voltage adjustable data to each the adjustable common voltage generating circuit.