Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor
    21.
    发明申请
    Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor 有权
    提供给网络处理器中的解析器和处理器访问外部协处理器

    公开(公告)号:US20120204002A1

    公开(公告)日:2012-08-09

    申请号:US13365679

    申请日:2012-02-03

    IPC分类号: G06F15/76 G06F9/06

    CPC分类号: H04L69/12

    摘要: A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.

    摘要翻译: 提供了一种用于共享由网络处理器的网络适配器中的解析器(解析器路径)使用的通信的机制,用于发送对要由外部协处理器执行的进程的请求。 解析器路径由网络处理器(软件路径)的处理器共享,以将请求发送到外部处理器。 该机制用于软件路径,包括由MMIO访问的控制地址和数据字段的请求邮箱,用于发送两种类型的消息,一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程, 用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。 网络的其他处理器轮询该标志直到设置,并获得协处理器结果的数据字段。

    System and Method for Multicore Communication Processing
    26.
    发明申请
    System and Method for Multicore Communication Processing 有权
    多核通信处理系统与方法

    公开(公告)号:US20080181245A1

    公开(公告)日:2008-07-31

    申请号:US11669419

    申请日:2007-01-31

    IPC分类号: H04L12/56

    CPC分类号: H04L47/50

    摘要: A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

    摘要翻译: 提供了一种用于数据处理设备之间的通信的多核处理的系统和方法。 利用说明性实施例的机制,提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外,这些技术还可以设计出多线程网络接口控制器(NIC)硬件,可有效地隐藏通过输入/输出(I / O)总线传输数据分组的直接存储器访问(DMA)操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行,以处理用于传输的数据分组,其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

    Host ethernet adapter for handling both endpoint and network node communications
    29.
    发明授权
    Host ethernet adapter for handling both endpoint and network node communications 失效
    主机以太网适配器,用于处理端点和网络节点通信

    公开(公告)号:US08576864B2

    公开(公告)日:2013-11-05

    申请号:US13011663

    申请日:2011-01-21

    IPC分类号: H04L12/28 H04J1/16

    CPC分类号: G06F15/1735

    摘要: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.

    摘要翻译: 提供主机以太网适配器(HEA)和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。 所述主机接口包括接收处理元件,所述接收处理元件包括接收处理器,接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列(CQ)的头部将网络节点模式中的多核处理器的线程调度完成队列元素(CQE)的完成队列调度器(CQS)。 该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统,选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务,在多核处理系统上运行设备驱动程序 所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务,选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务 模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。