公开(公告)号：US20160026826A1

公开(公告)日：2016-01-28

申请号：US14752677

申请日：2015-06-26

Applicant: Cryptography Research, Inc.

Inventor： Paul C. Kocher ,  Pankaj Rohatgi ,  Joshua M. Jaffe

IPC: G06F21/76 ,  G06F9/445

CPC classification number: G06F21/575 ,  G06F8/71 ,  G06F9/44505 ,  G06F12/1408 ,  G06F21/556 ,  G06F21/602 ,  G06F21/755 ,  G06F21/76 ,  G06F2212/402 ,  G06F2221/034 ,  G06F2221/2107 ,  G06F2221/2125 ,  G06F2221/2145 ,  H04L9/003 ,  H04L9/0631 ,  H04L9/085 ,  H04L9/0861 ,  H04L9/088 ,  H04L9/0894 ,  H04L9/16 ,  H04L9/3236 ,  H04L9/3247 ,  H04L63/0428 ,  H04L63/0869 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/56 ,  H04L2463/061

Abstract: A bitstream for configuration of a programmable logic device is received, the bitstream comprising a data segment and authentication data associated with the data segment. The programmable logic device computes a hash of the data segment. The programmable logic device compares the computed hash of the data segment with the authentication data. Configuration of the programmable logic device halts responsive to a determination that the computed hash of the data segment does not match the authentication data. Configuration of the programmable logic device using the data segment continues responsive to a determination that the computed hash of the data segment matches the authentication data.

Abstract translation: 接收用于配置可编程逻辑设备的比特流，所述比特流包括与所述数据段相关联的数据段和认证数据。 可编程逻辑器件计算数据段的散列。 可编程逻辑设备将计算出的数据段的散列与认证数据进行比较。 可编程逻辑设备的配置响应于所计算的数据段的散列与认证数据不匹配的确定停止。 使用数据段的可编程逻辑设备的配置继续响应于所计算的数据段的散列与认证数据匹配的确定。

公开(公告)号：US20150288524A1

公开(公告)日：2015-10-08

申请号：US14441998

申请日：2013-11-11

Applicant: CRYPTOGRAPHY RESEARCH INC.

Inventor： Joshua M. Jaffe

IPC: H04L9/32 ,  H04L9/14

CPC classification number: H04L9/3247 ,  H04L9/004 ,  H04L9/14 ,  H04L9/3252 ,  H04L2209/24 ,  H04L2209/72

Abstract: Methods and devices disclosed herein use techniques to resist glitch attacks when computing discrete-log based signatures. The methods and systems described herein replace the random nonce in conventional signature systems with a pseudorandom nonce derived in a deterministic way from some internal state information, such as a secret key or a counter, such that the nonce is not repeated. The methods and systems described herein may also use tests to verify that a glitch has not occurred or been introduced.

Abstract translation: 本文公开的方法和装置使用技术来抵抗在基于离散日志的签名时的毛刺攻击。 本文描述的方法和系统用诸如秘密密钥或计数器的某些内部状态信息以确定性方式导出的伪随机数替换常规签名系统中的随机随机数，从而不重复随机数。 本文描述的方法和系统还可以使用测试来验证毛刺没有发生或未被引入。

公开(公告)号：US20150280907A1

公开(公告)日：2015-10-01

申请号：US14737154

申请日：2015-06-11

Applicant: Cryptography Research, Inc.

Inventor： Paul C. Kocher ,  Pankaj Rohatgi ,  Joshua M. Jaffe

IPC: H04L9/00 ,  H04L9/16 ,  H04L9/06

CPC classification number: G06F21/575 ,  G06F8/71 ,  G06F9/44505 ,  G06F12/1408 ,  G06F21/556 ,  G06F21/602 ,  G06F21/755 ,  G06F21/76 ,  G06F2212/402 ,  G06F2221/034 ,  G06F2221/2107 ,  G06F2221/2125 ,  G06F2221/2145 ,  H04L9/003 ,  H04L9/0631 ,  H04L9/085 ,  H04L9/0861 ,  H04L9/088 ,  H04L9/0894 ,  H04L9/16 ,  H04L9/3236 ,  H04L9/3247 ,  H04L63/0428 ,  H04L63/0869 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/56 ,  H04L2463/061

Abstract: A device includes storage hardware to store a secret value and processing hardware coupled to the storage hardware. The processing hardware is to receive an encrypted data segment with a validator and derive a decryption key using the secret value and a plurality of entropy distribution operations. The processing hardware is further to verify, using the received validator, that the encrypted data segment has not been modified. The processing hardware is further to decrypt the encrypted data segment using the decryption key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.

Abstract translation: 设备包括存储硬件以存储与存储硬件耦合的秘密值和处理硬件。 处理硬件是使用验证器接收加密数据段，并使用秘密值和多个熵分布操作导出解密密钥。 处理硬件还使用接收到的验证器验证加密的数据段未被修改。 所述处理硬件还用于使用所述解密密钥对所述加密数据段进行解密，以响应于验证所述加密数据段未被修改而产生解密的数据段。