公开(公告)号：US10095477B2

公开(公告)日：2018-10-09

申请号：US15528069

申请日：2015-11-12

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F7/58

Abstract: The embodiments described herein describe a chain of pattern generators organized in a ring topology. Each of the pattern generators in the chain includes asynchronous digital logic and implements an update rule that generates a bidirectional pattern within the chain of pattern generators. The asynchronous digital logic of a first pattern generator in the chain asynchronously updates a next state of the first pattern generator based on at least (a) a current state of the first pattern generator, (b) a second state of a second pattern generator that is before the first pattern generator in the chain, and (c) a third state of a third pattern generator that is after the first pattern generator in the chain.

公开(公告)号：US09970986B2

公开(公告)日：2018-05-15

申请号：US14640180

申请日：2015-03-06

Applicant: Cryptography Research, Inc.

Inventor： Craig E. Hampel ,  Scott C. Best

IPC: G11C5/14 ,  G01R31/317 ,  G06F21/73 ,  G01R31/30

CPC classification number: G01R31/31719 ,  G01R31/3008 ,  G06F21/73

Abstract: Systems and methods for authenticating integrated circuits. An example integrated circuit may comprise: a plurality of functional units electrically coupled to a power source; and an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units.

公开(公告)号：US20240313986A1

公开(公告)日：2024-09-19

申请号：US18591554

申请日：2024-02-29

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H04L9/0869

Abstract: Technologies for generating an M-bit selection vector for a selector circuit that receives as input M binary values from a set of entropy-generation elements and outputs N binary values responsive to the M-bit selection vector are described. N bits in the M-bit selection vector are set to a first logic state, and M-N bits of the M-bit selection vector are set to a second logic state. A determination of which N bits in the M-bit selection vector are set to the first logic state is determined by a process. The process includes determining an accumulated Hamming weight value for M bit positions of the M-bit selection vector using K samples and identifying N bit positions in the M-bit selection vector using the accumulated Hamming weight values. The process sets the N bits corresponding to the N bit positions in the M-bit selection vector to the first logic state.

公开(公告)号：US11568114B2

公开(公告)日：2023-01-31

申请号：US17269219

申请日：2019-08-15

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F30/327 ,  G06F21/14 ,  H03K19/20

Abstract: Described are technologies of all-digital camouflage circuits. The camouflage circuit can include a first chain of inverters, synthesized with a first standard cell with a first transistor threshold, and a second chain of inverters, synthesized with a second standard cell with a second transistor threshold that is different than the first transistor threshold. A first flip-flop receives a first output of the first chain as a data input and a second output of the second chain as a clock input. A second flip-flop receives the second output as a data input and the first output of the first chain as a clock input. Given the different transistor thresholds, one flip-flop always outputs an active signal that corresponds to an input signal applied to the first chain and the second chain. The other flip-flop always output a constant signal, such an always low signal.

公开(公告)号：US11502047B2

公开(公告)日：2022-11-15

申请号：US16645353

申请日：2018-09-07

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/08

Abstract: The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.

公开(公告)号：US20220269827A1

公开(公告)日：2022-08-25

申请号：US17636831

申请日：2020-09-04

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best ,  Christopher Leigh Rodgers

IPC: G06F21/76

Abstract: A pattern detector circuit is provided in a security chip, wherein the pattern detector circuit monitors accesses of a plurality of configuration registers, each of the plurality of configuration registers having a corresponding address. In response to receiving from a host a predefined sequence of accesses of the plurality of configuration registers for one or more operations to the plurality of configuration registers, a processor in the pattern detector circuit determines a value indicative of a current version of a netlist for the security chip. The determined value is made available to be obtained by a read operation by the host at a specific configuration register address.

公开(公告)号：US20220237281A1

公开(公告)日：2022-07-28

申请号：US17612527

申请日：2020-05-21

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best

IPC: G06F21/44 ,  G06F12/14

Abstract: A block of data is provided from a verifier module to an authenticator module, the size of the block being correlated with one or more desired characteristics of the authenticator module. The verifier module receives a response from the authenticator module, the response comprising data result derived from a calculation involving the challenge value and the block of data. The verifier module verifies whether the response is indicative of the one or more desired characteristics of the authenticator module.

公开(公告)号：US11301216B2

公开(公告)日：2022-04-12

申请号：US17000121

申请日：2020-08-21

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F7/58

Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.

公开(公告)号：US20210035924A1

公开(公告)日：2021-02-04

申请号：US16645353

申请日：2018-09-07

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: H01L23/00 ,  H04L9/08 ,  G06F21/87

Abstract: The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.

公开(公告)号：US10897363B2

公开(公告)日：2021-01-19

申请号：US15771076

申请日：2016-11-16

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Joel Patrick Wittenauer ,  Scott C. Best ,  Paul Carl Kocher

IPC: H04L9/32

Abstract: A table key capable of decrypting a first table from a plurality of encrypted tables may be received. Each of the encrypted tables may include at least one pair of values corresponding to a challenge value and a response value. A request to authenticate a secondary device may be received and in response to the request to authenticate the secondary device, a challenge value obtained by using the table key to decrypt an entry in the first table may be transmitted to the secondary device. A second challenge value may be transmitted to the secondary device and a cryptographic proof may be received from the secondary device. The validity of the cryptographic proof received from the secondary device may be authenticated based on the second challenge value and the response value obtained by using the table key to decrypt the entry in the first table.