公开(公告)号：US11996167B2

公开(公告)日：2024-05-28

申请号：US17636982

申请日：2020-08-14

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Mark Evan Marson ,  Joel Wittenauer

IPC: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/0035

Abstract: A random number generator selects addresses while a ‘scoreboard’ bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an address has already been output, a second address which has not been used yet is output rather than the randomly selected one. The second address may be selected from nearby addresses that have not already been output.

公开(公告)号：US11329010B2

公开(公告)日：2022-05-10

申请号：US16838577

申请日：2020-04-02

Applicant: Cryptography Research, Inc

Inventor： Scott C. Best ,  Ming Li ,  Gary B. Bronner ,  Mark Evan Marson

IPC: H01L23/00

Abstract: An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.

公开(公告)号：US20210342509A1

公开(公告)日：2021-11-04

申请号：US17269219

申请日：2019-08-15

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F30/327 ,  H03K19/20 ,  G06F21/14

Abstract: Described are technologies of all-digital camouflage circuits. The camouflage circuit can include a first chain of inverters, synthesized with a first standard cell with a first transistor threshold, and a second chain of inverters, synthesized with a second standard cell with a second transistor threshold that is different than the first transistor threshold. A first flip-flop receives a first output of the first chain as a data input and a second output of the second chain as a clock input. A second flip-flop receives the second output as a data input and the first output of the first chain as a clock input. Given the different transistor thresholds, one flip-flop always outputs an active signal that corresponds to an input signal applied to the first chain and the second chain. The other flip-flop always output a constant signal, such an always low signal.

公开(公告)号：US20210048985A1

公开(公告)日：2021-02-18

申请号：US17000121

申请日：2020-08-21

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F7/58

Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.

公开(公告)号：US12013751B2

公开(公告)日：2024-06-18

申请号：US16972560

申请日：2019-06-05

Applicant: Cryptography Research, Inc.

Inventor： Mark Evan Marson ,  Scott C. Best ,  Helena Handschuh ,  Winthrop John Wu

IPC: G06F11/10 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F11/10 ,  H04L9/0866 ,  H04L9/3278

Abstract: A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.

公开(公告)号：US10754620B2

公开(公告)日：2020-08-25

申请号：US16707349

申请日：2019-12-09

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F7/58

Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.

公开(公告)号：US10303623B2

公开(公告)日：2019-05-28

申请号：US15469999

申请日：2017-03-27

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Brent S. Haukness ,  Carl W. Werner

IPC: G06F12/02 ,  G06F12/14 ,  G06F21/44 ,  G06F21/55 ,  G06F21/75 ,  G06F21/79 ,  G06F3/06 ,  G11C13/00 ,  G11C7/24 ,  H04L9/00 ,  H04L9/08 ,  H04L9/32

Abstract: A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. In response to the request to perform the authentication operation, the authentication component may access the first data stored at the first non-volatile memory and the second data stored at the second non-volatile memory and determine whether the second data stored at the second non-volatile memory has become unreliable based on a memory disturbance condition. In response to determining that the second data stored at the second non-volatile memory has become unreliable, a corrective action associated with the first data stored at the first non-volatile memory may be performed.

公开(公告)号：US20240345916A1

公开(公告)日：2024-10-17

申请号：US18644084

申请日：2024-04-23

Applicant: Cryptography Research, Inc.

Inventor： Mark Evan Marson ,  Scott C. Best ,  Helena Handschuh ,  Winthrop John Wu

IPC: G06F11/10 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F11/10 ,  H04L9/0866 ,  H04L9/3278

Abstract: A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.

公开(公告)号：US20230163962A1

公开(公告)日：2023-05-25

申请号：US17989594

申请日：2022-11-17

Applicant: Cryptography Research, Inc.

Inventor： Winthrop Wu ,  Scott C. Best

IPC: H04L9/08 ,  H04L9/00

CPC classification number: H04L9/0869 ,  H04L9/003 ,  H04L9/0822

Abstract: Technologies for selectively distributing a same random number to multiple cryptographic circuits are described. One apparatus includes a plurality of cryptographic circuits. Each of the plurality of cryptographic circuits is to receive a random number for differential power analysis (DPA) protection of a cryptographic operation. At least two of the plurality of cryptographic circuits are configured to selectively use a same random number.

公开(公告)号：US20220358253A1

公开(公告)日：2022-11-10

申请号：US17633534

申请日：2020-08-21

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best

IPC: G06F21/87

Abstract: A resistor mesh with distributed sensing points is provided in a security chip as an anti-tamper shield. An analog multiplexing circuit is configured to receive a pair of digital selection values created by an algorithm processing circuit, and produce a respective differential voltage formed by a pair of voltages obtained at a pair of selected sensing points within the resistor mesh corresponding to the pair of digital selection values. Each differential voltage is converted into a corresponding digital output value. An algorithm processing circuit is configured to receive a respective digital output value associated with each pair of digital selection values and derive a binary value based on a subset of the digital output values, wherein the binary value is unique to the security chip.