公开(公告)号：US10013310B2

公开(公告)日：2018-07-03

申请号：US15241808

申请日：2016-08-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho Han ,  Young-Su Kwon ,  Kyoung Seon Shin ,  Kyung Jin Byun ,  Nak Woong Eum

IPC: G06F11/10 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0895

CPC classification number: G06F11/1076 ,  G06F11/1044 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/1032 ,  Y02D10/13

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

公开(公告)号：US09529654B2

公开(公告)日：2016-12-27

申请号：US14547301

申请日：2014-11-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young Su Kwon ,  Jin Ho Han ,  Kyung Jin Byun

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/18

CPC classification number: G06F11/0772 ,  G06F11/0721 ,  G06F11/183

Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。