公开(公告)号：US4292668A

公开(公告)日：1981-09-29

申请号：US8002

申请日：1979-01-31

申请人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F3/00

CPC分类号： G06F13/362 ,  G06F13/285

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 在系统内提供了：解决对一个或多个公共总线的冲突请求，CPU确认DMC请求，识别请求的IOC到CPU，从主存储器或IOC访问一个单元的数据，并传送 数据单位到IOC或主存储器。

公开(公告)号：US4218739A

公开(公告)日：1980-08-19

申请号：US736657

申请日：1976-10-28

申请人： Virendra S. Negi ,  Ming T. Miu

发明人： Virendra S. Negi ,  Ming T. Miu

IPC分类号： G06F9/48 ,  G06F9/18

CPC分类号： G06F9/4812 ,  G06F9/4825

摘要： Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.

摘要翻译： 数据处理器内部产生的中断（内部中断）和从处理器耦合的外部设备（外部中断）接收到的中断被优先考虑，除非被禁止，以产生中断信号，以用于寻址维修特定的程序 最高优先级请求内部或外部中断。 所有进一步的中断在服务中断所需的时间内被抑制，并且根据中断的类型，内部或外部中断可能被抑制一个或两个指令时间用于调试目的或在计算机程序控制下，对于特定的 操作。