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公开(公告)号：US4127768A
公开(公告)日：1978-11-28
申请号：US756298
申请日：1977-01-03
申请人： Virendra S. Negi , Ming T. Miu
发明人： Virendra S. Negi , Ming T. Miu
IPC分类号： G06F11/267 , G06F11/04
CPC分类号： G06F11/2236
摘要： Diagnostic testing of a central processor is provided in conjunction with a memory coupled with the processor without any requirement for an input device such as a tape or card reader. Local storage of a test program is provided in the processor which, under the control of a local control store, enables the transfer of the test program to the memory for execution. The central processor may thus be given an initial test to insure a basic performance level.
摘要翻译： 结合与处理器耦合的存储器提供中央处理器的诊断测试，而不需要诸如磁带或读卡器之类的输入设备。 在处理器中提供了测试程序的本地存储器，其在本地控制存储器的控制下能够将测试程序传送到存储器以供执行。 因此，可以对中央处理器进行初始测试以确保基本性能水平。
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公开(公告)号：US4086474A
公开(公告)日：1978-04-25
申请号：US728093
申请日：1976-09-30
申请人： Virendra S. Negi , Ming T. Miu
发明人： Virendra S. Negi , Ming T. Miu
CPC分类号： G06F7/5272
摘要： Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign of a bit in a predetermined bit location of the multiplier as shifted in a shift register, the multiplier and the multiplicand are operated on by either a shift operation or operated on by a shift and add operation.
摘要翻译： 两个数字相乘在一起，而无需首先将它们中的任一个（如果为负）更改为正数，从而最小化乘法过程所需的时间。 在乘法中，取决于在移位寄存器中移位的乘法器的符号和乘法器的预定位位置中的位的符号，乘法器和被乘数通过移位操作进行操作或由 移位和添加操作。
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3.发明授权Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus 失效通过异步公共总线网络耦合数据处理设备进行数据传输的同步技术
公开(公告)号：US4050097A
公开(公告)日：1977-09-20
申请号：US727194
申请日：1976-09-27
申请人： Ming T. Miu , Virendra S. Negi , Richard A. Lemay
发明人： Ming T. Miu , Virendra S. Negi , Richard A. Lemay
CPC分类号： G06F1/08 , G06F13/4213
摘要： Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.
摘要翻译： 数据传输同步在数据处理系统中通过传送单元实现，每当传输尝试时，能够进行时钟周期失速机制，在接收到来自接收单元的预定响应时禁用这种机制，实际产生时钟周期失速的机制如果 这种预定响应被延迟超过时钟周期的持续时间。 此外，在预期接收到信息之前，在接收单元中启用这种停止机制，并且如果这样的响应如此延迟，则实际上产生时钟周期停滞。
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4.发明授权
公开(公告)号：US4218739A
公开(公告)日：1980-08-19
申请号：US736657
申请日：1976-10-28
申请人： Virendra S. Negi , Ming T. Miu
发明人： Virendra S. Negi , Ming T. Miu
CPC分类号： G06F9/4812 , G06F9/4825
摘要： Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.
摘要翻译： 数据处理器内部产生的中断（内部中断）和从处理器耦合的外部设备（外部中断）接收到的中断被优先考虑，除非被禁止，以产生中断信号，以用于寻址维修特定的程序 最高优先级请求内部或外部中断。 所有进一步的中断在服务中断所需的时间内被抑制，并且根据中断的类型，内部或外部中断可能被抑制一个或两个指令时间用于调试目的或在计算机程序控制下，对于特定的 操作。
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5.发明授权Data processor having units carry and tens carry apparatus supporting a decimal multiply operation 失效具有单元的数据处理器进位和十进位装置支持十进制乘法运算
公开(公告)号：US4484300A
公开(公告)日：1984-11-20
申请号：US219810
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
CPC分类号： G06F7/4915
摘要： A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit. The multiplexer selects the output of the tens carry flip-flop for adding the tens carry during the next tens cycle in which the next tens product decimal digit is added to a next higher order partial product decimal digit.
摘要翻译： 数据处理系统通过将乘数十进制数和乘数十进制数的乘积存储在只读存储器中并将部分乘积十进制数字存储在寄存器中来执行十进制乘法指令。 单位产品十进制数字在一个周期内从只读存储器读取，并添加到部分乘积十进制数字。 结果单位进位存储在单位进位触发器中。 在另一个周期内，从只读存储器读取十位数十进制数，并将其加到较高阶部分乘积十进制数字。 结果十进位存储在十进位触发器中。 多路复用器在下一个单位周期内，将下一个单位乘积十进制数字加到较高阶部分乘积十进制数字中，选择输入单元的单元进位触发器来添加单位进位。 多路复用器选择十位进位触发器的输出，在下一个十位周期中将下一个十位乘数十进制数字加到下一个高阶部分乘积十进制数字的十进位。
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6.发明授权
公开(公告)号：US4410984A
公开(公告)日：1983-10-18
申请号：US250820
申请日：1981-04-03
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.
摘要翻译： 耦合到公共总线的微程序控制商业指令处理器执行诊断微程序，以检查公共总线接口寄存器及其相关内部寄存器的数据路径。 诊断微程序的预定微字的解码位产生一个信号，该信号在一个微字循环期间通过接口寄存器顺序地将存储在第一内部寄存器中的包含多个字节的预定数据字传送到第二个内部寄存器。 设备为选定的字节产生不良的奇偶校验。 后续微词比较第一和第二内部寄存器的内容，并验证“坏”奇偶校验的检测。
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7.发明授权Local bus interface for controlling information transfers between units in a central subsystem 失效用于控制中央子系统中单元之间的信息传输的本地总线接口
公开(公告)号：US4323967A
公开(公告)日：1982-04-06
申请号：US140622
申请日：1980-04-15
CPC分类号： G06F13/364 , G06F12/084 , G06F13/4059
摘要： In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.
摘要翻译： 在数据处理系统中，中央子系统包括多个专用处理单元，其中一个处理单元用作中央子系统内的控制处理单元。 处理单元耦合到公共子系统总线，用于在中央子系统内传送数据，控制信息和地址信息。 子系统总线的访问由总线控制单元分配，总线控制单元还将中央子系统与诸如包括在数据处理系统中的系统存储器或系统I / O设备的其他处理单元接口。
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公开(公告)号：US4667288A
公开(公告)日：1987-05-19
申请号：US509898
申请日：1983-06-30
CPC分类号： G11C29/88 , G06F11/073 , G06F11/0772 , G06F11/2289 , G06F12/126 , G06F11/10 , G06F12/00 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.
摘要翻译： 其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于来自目录错误检查电路的错误信号而选择性地降级高速缓存操作到被检测为没有错误的那些级别。 耦合到目录错误检查装置的测试控制装置操作以响应于从中央处理单元接收的命令选择性地启用和禁用目录错误检查电路，以便能够使用高速缓存系统的高速缓存目录和其他部分的测试 常用测试程序。
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公开(公告)号：US4462072A
公开(公告)日：1984-07-24
申请号：US250810
申请日：1981-04-03
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
CPC分类号： G06F11/073 , G06F1/08 , G06F11/0721 , G06F11/0793
摘要： A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.
摘要翻译： 通过停止自由运行的时钟信号，在CIP和主存储器之间的信息传送期间，微程序商业指令处理器（CIP）被置于停止模式。 当信息传输完成时，自由运行的时钟周期。 如果主存储器指示错误状况，则自由运行的时钟信号在一个周期后再次停止，以允许CIP中的固件处理该错误。
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公开(公告)号：US4271484A
公开(公告)日：1981-06-02
申请号：US841
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
CPC分类号： G06F9/3885 , G06F11/302 , G06F11/3093 , G06F9/30058 , G06F9/30094
摘要： Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.
摘要翻译： 在指令执行周期期间表示被测状态的过去和现在状态的信号以及表示执行周期的信号被用作施加到存储器的地址信号，所述存储器馈送输出以控制双稳态元件 。 双稳态元件设置为存储器输出信号的状态，并提供表示被测状态的过去状态的地址信号。 存储器被编码以在其输出处响应控制双稳态元件的信号，使得一旦检测到被测状态的给定状态并将其存储在双稳态元件中，则后者被禁止切换，而不管条件下的任何进一步变化如何 在当前指令执行周期内进行测试。
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