公开(公告)号：US4127768A

公开(公告)日：1978-11-28

申请号：US756298

申请日：1977-01-03

申请人： Virendra S. Negi ,  Ming T. Miu

发明人： Virendra S. Negi ,  Ming T. Miu

IPC分类号： G06F11/267 ,  G06F11/04

CPC分类号： G06F11/2236

摘要： Diagnostic testing of a central processor is provided in conjunction with a memory coupled with the processor without any requirement for an input device such as a tape or card reader. Local storage of a test program is provided in the processor which, under the control of a local control store, enables the transfer of the test program to the memory for execution. The central processor may thus be given an initial test to insure a basic performance level.

摘要翻译： 结合与处理器耦合的存储器提供中央处理器的诊断测试，而不需要诸如磁带或读卡器之类的输入设备。 在处理器中提供了测试程序的本地存储器，其在本地控制存储器的控制下能够将测试程序传送到存储器以供执行。 因此，可以对中央处理器进行初始测试以确保基本性能水平。

公开(公告)号：US4086474A

公开(公告)日：1978-04-25

申请号：US728093

申请日：1976-09-30

申请人： Virendra S. Negi ,  Ming T. Miu

发明人： Virendra S. Negi ,  Ming T. Miu

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/54

CPC分类号： G06F7/5272

摘要： Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign of a bit in a predetermined bit location of the multiplier as shifted in a shift register, the multiplier and the multiplicand are operated on by either a shift operation or operated on by a shift and add operation.

摘要翻译： 两个数字相乘在一起，而无需首先将它们中的任一个（如果为负）更改为正数，从而最小化乘法过程所需的时间。 在乘法中，取决于在移位寄存器中移位的乘法器的符号和乘法器的预定位位置中的位的符号，乘法器和被乘数通过移位操作进行操作或由 移位和添加操作。

公开(公告)号：US4050097A

公开(公告)日：1977-09-20

申请号：US727194

申请日：1976-09-27

申请人： Ming T. Miu ,  Virendra S. Negi ,  Richard A. Lemay

发明人： Ming T. Miu ,  Virendra S. Negi ,  Richard A. Lemay

IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F1/08 ,  G06F13/4213

摘要： Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

摘要翻译： 数据传输同步在数据处理系统中通过传送单元实现，每当传输尝试时，能够进行时钟周期失速机制，在接收到来自接收单元的预定响应时禁用这种机制，实际产生时钟周期失速的机制如果 这种预定响应被延迟超过时钟周期的持续时间。 此外，在预期接收到信息之前，在接收单元中启用这种停止机制，并且如果这样的响应如此延迟，则实际上产生时钟周期停滞。

公开(公告)号：US4218739A

公开(公告)日：1980-08-19

申请号：US736657

申请日：1976-10-28

申请人： Virendra S. Negi ,  Ming T. Miu

发明人： Virendra S. Negi ,  Ming T. Miu

IPC分类号： G06F9/48 ,  G06F9/18

CPC分类号： G06F9/4812 ,  G06F9/4825

摘要： Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.

摘要翻译： 数据处理器内部产生的中断（内部中断）和从处理器耦合的外部设备（外部中断）接收到的中断被优先考虑，除非被禁止，以产生中断信号，以用于寻址维修特定的程序 最高优先级请求内部或外部中断。 所有进一步的中断在服务中断所需的时间内被抑制，并且根据中断的类型，内部或外部中断可能被抑制一个或两个指令时间用于调试目的或在计算机程序控制下，对于特定的 操作。

公开(公告)号：US4321665A

公开(公告)日：1982-03-23

申请号：US8121

申请日：1979-01-31

申请人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

发明人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/40 ,  G06F3/00

CPC分类号： G06F13/4013

摘要： In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

摘要翻译： 在包括中央处理单元（CPU）的数据处理系统中，主存储器和连接到公共总线信息的多个输入/输出控制器（IOC）可以在主存储器和CPU以及主存储器和IOC之间传送。 在CPU内部提供逻辑，以便在公共总线的数据线上对齐一个数据字节，使得它可以从主存储器从数据线中取出，并写入多字节字而无需进一步对齐。 在CPU中提供逻辑以从从主存储器读取的数据的多字节字提取出公共总线数据线上相应的数据字节并将其对准在公共总线数据线上，使得IOC可以传递数据 字节到外围设备，无需进一步对齐。

公开(公告)号：US4317169A

公开(公告)日：1982-02-23

申请号：US12081

申请日：1979-02-14

申请人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

发明人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

IPC分类号： G06F12/00 ,  G11C11/406 ,  G06F13/00

CPC分类号： G11C11/406

摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

摘要翻译： 在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号， 可以执行存储器刷新操作。 逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。 此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。 在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

公开(公告)号：US4300194A

公开(公告)日：1981-11-10

申请号：US8004

申请日：1979-01-31

申请人： John J. Bradley ,  Ming T. Miu ,  Jian-Kuo Shen

发明人： John J. Bradley ,  Ming T. Miu ,  Jian-Kuo Shen

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F3/04

CPC分类号： G06F13/362

摘要： Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

摘要翻译： 提供多个公共总线用于在数据处理系统中耦合多个单元以便在其间传送信息。 中央处理单元（CPU）响应于从希望使用公共总线的各个单元接收的总线请求，将多个公共总线分配给单元之一。 通过使用源自CPU的定时信号以同步方式产生总线请求，该定时信号串联连接在多个公共总线中的每一个上的一个或多个单元之间。

公开(公告)号：US5051894A

公开(公告)日：1991-09-24

申请号：US294528

申请日：1989-01-05

申请人： Forrest M. Phillips ,  Thomas F. Joyce ,  Ming T. Miu

发明人： Forrest M. Phillips ,  Thomas F. Joyce ,  Ming T. Miu

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0886 ,  G06F12/10 ,  G06F12/1491 ,  G06F2212/655

摘要： In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.

公开(公告)号：US4293908A

公开(公告)日：1981-10-06

申请号：US8001

申请日：1979-01-31

申请人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理单元（CPU）。 提供逻辑用于在直接存储器访问（DMA）数据传输操作期间传送一个数据单元，其中请求IOC请求CPU的DMA数据传输。 在系统内提供的装置是：解决对一个或多个公共总线的冲突请求，CPU确认DMA请求，IOC将要写入数据单元的位置的地址传送到主存储器，之后是 数据单元或IOC传输要从其读取数据单元的主存储器中的位置的地址，然后接收从主存储器读取的数据单元。

公开(公告)号：US4785398A

公开(公告)日：1988-11-15

申请号：US811044

申请日：1985-12-19

申请人： Thomas F. Joyce ,  Ming T. Miu ,  Jian-Kuo Shen ,  Forrest M. Phillips

发明人： Thomas F. Joyce ,  Ming T. Miu ,  Jian-Kuo Shen ,  Forrest M. Phillips

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/0882 ,  G06F12/0831 ,  G06F12/1063

摘要： A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

摘要翻译： 多处理器计算机系统包括主存储器和多个中央处理单元（CPU），其经由公共总线网络连接以共享主存储器。 每个CPU都有指令和数据缓存单元，每个单元都以页面为单位进行组织，以便与用户进程完全兼容。 每个高速缓存单元包括多个内容可寻址存储器（CAM）和可直接寻址的存储器（RAM），其被组织以组合以组合基于页面的数据或指令的关联和直接映射。 响应于CPU地址的输入CAM提供缓存地址，该缓存地址包括用于识别所有所需信息驻留在其他存储器中的页面级别号码，用于处理与该页面有关的请求。 该组织允许以改进的速度和降低的复杂性处理虚拟或物理地址，并且能够检测和消除一致性和同义词问题。