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公开(公告)号:US20220415558A1
公开(公告)日:2022-12-29
申请号:US17358354
申请日:2021-06-25
Applicant: Google LLC
Inventor: Chenhao Nan , Houle Gan , Runruo Chen , Qiong Wang , Xin Li
Abstract: The subject matter described herein provides systems and techniques for the integration of TLVR technology in a vertical power VR module. A multiple-secondary TLVR topology using a controlled leakage inductance in the place of a separate compensation inductor, Lc, may be employed for the vertical power VR module. In addition, the capacitance inside the device to which the TLVR based vertical power VR module supplies power, rather than an output capacitance board, may be used in order to allow the module to be a single layer. Example structures that may include one or more primary windings and/or one or more secondary windings for each of possibly multiple linked phases of the TLVR based module are provided. The windings may be formed using traditional copper windings or printed circuit board (PCB) copper trace winding.
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公开(公告)号:US20190068061A1
公开(公告)日:2019-02-28
申请号:US16170452
申请日:2018-10-25
Applicant: Google LLC
Inventor: Shuai Jiang , Chee Yee Chung , Xin Li
IPC: H02M3/158
Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.
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公开(公告)号:US10141849B1
公开(公告)日:2018-11-27
申请号:US15675285
申请日:2017-08-11
Applicant: Google LLC
Inventor: Shuai Jiang , Chee Yee Chung , Xin Li
IPC: H02M3/158
Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.
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